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Intel® Centrino® Duo Processor Technology
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Home  ›  Technology and Research  ›  Intel® Technology Journal  ›  Intel® Centrino® Duo Mobile Technology
Intel® Centrino® Duo Mobile Technology
Intel® Technology Journal
Featuring Intel's recent
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Intel® Centrino® Duo Mobile Technology
Volume 10    Issue 02    Published May 15, 2006
ISSN 1535-864X    DOI: 10.1535/itj.1002.04

  Section 11 of 11  
System memory power and thermal management in platforms built on Intel® Centrino® Duo mobile technology
Authors’ biographies


Jayesh Iyer
Jayesh Iyer joined Intel’s Mobile Platforms group in 2003. He is part of the Mobile Platform Architecture and Development team, designing Customer Reference boards for next-generation Intel® processors and chipsets. He also works on platform memory power performance initiatives (such as DT in SPD and TS on DIMM) and memory profiling. He has also worked as a research intern at the Indian Space Research Organization. Jayesh received his B.E. degree in Instrumentation & Control Engineering from Gujarat University and his M.S. degree in Electrical Engineering and Computer Engineering from Drexel University, Philadelphia. His e-mail is jayesh.iyer at intel.com.

Corrine Hall
Corinne Hall joined Intel in 2001 and has worked in both the Desktop Products Organization as well as the Mobile Platform Group. Her current responsibilities include Thermal Sensor on DIMM enabling as well as other memory thermal and power-related activities for DDR2 and DDR3. Corinne received a B.S.E.E. degree in Computer Engineering from Oregon State University. Her e-mail is corinne.l.hall at intel.com.

Jerry Shi
Jerry Shi has been with Intel for seven years, working as a platform/memory architect. He designed the first Intel® Networking Processor-based cPCI system for demonstration at SuperComm. At Intel he also designed the first set-top-box which could do Picture-in-Picture MPEG playback. He also holds patents related to memory architecture. Prior to Intel, he worked for Philips Semiconductors, Hyundai Electronics, and Oak Technology. Jerry received a B.S.E.E. degree in Computer Science and Engineering from Tsinghua University, China and an M.S.E.E. degree in Electrical Engineering from UMASS at Amherst. His e-mail is jerry.shi at intel.com.

Yuchen Huang
Yuchen Huang is a staff platform memory power Engineer in Intel's Technology Manufacturing Group. She joined Intel in1994, and has held various platform design positions there as Intel’s Desktop Product Group platform memory power and performance initiatives owner and as a platform interconnect designer. Currently, Yuchen leads a cross-divisional engineering team within Intel that addresses memory power, thermal, and performance platform challenges. Yuchen received a B.S.E.E. degree in Electrical Engineering from Zhejiang University, China and a M.S.E.E. degree in Electrical Engineering from Portland State University. Her e-mail is yuchen.huang at intel.com.

 

  Section 11 of 11  

In this article
Abstract
Introduction
Delta Temperature (DT) in Serial Presence Detect (SPD)
Need for system memory throttling
DT in SPD
TS on DIMM
Results
Summary
Acknowledgments
References
Authors' biographies
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