DT in SPD is a throttling technique that gives a huge performance benefit to platforms that do not have a physical thermal sensor on the memory module. Before going into the details of DT in SPD, let’s briefly look into the throttling methodology followed in the chipsets of previous-generation platforms.

A DDRx4-based memory subsystem, as a major power-consuming component on a platform, is peculiar in that its power consumption is difficult to predict in reality. The reason for this is that memory vendors have their own unique processes and design technologies. This results in large variations among different DRAM vendors in power consumption given a fixed device density and speed for each particular DDRx technology. Figure 3 shows the differences in the Burst read current (IDD4R) of the best-, typical-, and worst-case memory supplier (DDR2 512 MB DRAM) across three different memory speeds. As the memory device power is a function of its IDD numbers, a huge difference in the IDD numbers between the best-case and worst-case memory suppliers translates into a huge difference in their power consumption.

Figure 3: Power differences between best-, typical- and worst-case memory suppliers
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In the previous-generation mobile platforms, the system could tell the memory type (device density, number of ranks, device width) and its vendor by retrieving the data from a small EEPROM (called SPD) on each memory module during boot up. But this doesn’t indicate how much power the module consumes. Also these platforms did not have a thermal sensor on the DRAM modules to monitor their temperature, and hence their temperature needed to be tracked by some alternative means.

The VTS throttle mechanism (implemented for the first time in the Mobile Intel® 915GMCH Express Chipset) provides this alternative solution. VTS predicts the memory case temperature based on the memory access type at each clock cycle. The power estimates for each of the memory access types are programmed in the chipsets throttle weights register [2] and a discretized lumped thermal capacitance model [6] is used to predict the time-varying temperature response to the power consumption. The chipsets in these platforms implemented a throttling methodology without any feedback on power or temperature from the memory module. Without this knowledge of power consumption from the memory module, the system (VTS throttle mechanism implemented in the chipset) was forced to assume the worst-case power consumption for design safety. Thus memory thermal limits (throttling threshold value) were set based on the worst-case supplier’s power data. This approach thus resulted in over-guard-banding5 and over-memory-throttling. The memory performance degrades as low-power memory modules are treated as the worst-case modules.

Now the inevitable question is, how can a system, especially when it does not have a physical thermal sensor on the memory modules, accurately and cost-effectively tell memory power consumption to avoid over throttling memory, i.e., how can it reduce the guardband? It can by using DT in SPD.

Overview of DT in SPD

DT in SPD is a power/thermal prediction scheme providing DRAM power/thermal data in the SPD on the module. It stores key temperature rise data for each memory access type (Reads, Writes, Self-Refresh, etc.) and DRAM maximum case temperature limit data (Tcasemax) in the SPD on the memory module. The system (VTS throttling mechanism implemented in the chipset) uses this information to better estimate the temperature of the DRAM devices and to determine when throttling is necessary. When process shrinks or other power optimizations occur and DRAM power dissipation decreases, the system uses the information stored in SPD to reduce memory throttling and regain system performance.

Usage Model

Memory module vendors report the delta temperature rise parameters and Tcasemax in SPD. These parameters are read by the BIOS from the SPD at boot time. Subsequently, the system adjusts memory throttle limits based on these parameters.

Performance Benefit of DT in SPD

DT in SPD greatly reduces the guardband and helps recover the bandwidth as compared to the throttling methodologies implemented in chipsets in the previous platforms, which set memory thermal limits (throttling threshold value) based on the worst-case supplier’s power data. A lab study was done on thin and light laptops using memory modules of different configurations from different vendors. As mentioned earlier, there is a huge difference in the power numbers between different vendors (for the same configuration). The best-case, typical-case, and worst-case DRAM vendors (for each configuration of the memory) in terms of power numbers were used for the study. A chipset stress utility based on Windows*, which generates very high traffic (almost all Page hits) on the memory bus, was used to exercise the system memory. Figures 4 and 5 each give the comparison of performance achieved running the utility with 30% Writes and 70% Reads on the thin and light design. It shows the sustained bandwidth across different memory throttle limits using the two throttling control methodologies: 1) with DT in SPD; 2) without DT in SPD (using worst-case supplier power data).

Figure 4: Sustained bandwidth across memory throttle limits (best-case supplier)
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Figure 5: Sustained bandwidth across memory throttle limits (typical-case supplier)
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The results in Figure 4 show that a typical-case memory supplier gives a performance benefit of 8% (in terms of sustained bandwidth) using DT in SPD. But for measurements done on a best-case memory supplier, the performance benefit goes up to 30% (in terms of sustained bandwidth) using DT in SPD as shown in Figure 5. Thus the results clearly demonstrate that using DT in SPD greatly reduces the guardband and helps recover the bandwidth. This enhances memory performance, especially for very low-power memory modules (best-case supplier).

Though DT in SPD has its benefits in systems that don’t have a physical thermal sensor on the memory modules, it is still an open-loop throttling mechanism as it does not actually know the operating temperature of the DIMM. Therefore it must always assume the notebook is operating under the maximum allowed room ambient temperature, which is typically considered to be 35°C for mobile environments. So if a notebook is actually running in an environment where the room ambient temperature is only 20°C, then DT in SPD actually assumes it is running at 35°C and will initiate throttling ~15°C sooner than it is needed, thereby losing potential performance that could have been obtained had the system not initiated throttling so soon.

TS on DIMM provides a much more robust thermal throttling mechanism while optimizing performance by offering reduced guardband over other existing methods. The following section describes in detail the concept, implementation details, and the performance benefit achieved using TS on DIMM.