CMP Implementation in Systems Based on the Intel® Core™ Duo Processor

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Volume 10 Issue 02 Published May 15, 2006
ISSN 1535-864X DOI: 10.1535/itj.1002.02

Section 9 of 10

CMP Implementation in Systems Based on the Intel® Core™ Duo Processor

REFERENCES

[1] Gochman et Al., "Introduction to Intel® Core™ Duo Processor Architecture," in Intel Technology Journal, Volume 10, Issue 2, 2006.

[2] Naveh et al., "Power and Thermal Control in the Intel® Core™ Duo Processor," in Intel Technology Journal, Volume 10, Issue 2, 2006.

[3] IA-32 Intel® Architecture Software Developer’s Manual Volume 3A: System Programming Guide, Part 1

[4] IA-32 Intel® Architecture Optimization Reference Manual, in http://www.intel.com/design/Pentium4/manuals/248966.htm

Section 9 of 10

In This Article


	Abstract

	Introduction

	CMP Implementation and Design Considerations

	The Protocol

	Performance Measurements

	Comparing Split Cache with Shared Cache

	Optimization Opportunities For Intel® Core™ Duo Processor

	Conclusion and Remarks

	References

	Authors' Biographies