Intel® Core™ Duo processor-based technology implements shared cache-based CMP microarchitecture in order to maximize the performance of both ST and MT applications (assuming the same L2 cache size). Figure 3 describes the general structure of our implementation. The figure shows the following:

• Each core is assumed to have an independent APIC unit to be presented to the OS as a "separate logical processor."
• From an external point of view the system behaves like a Dual Processor (DP) system.
• From the software point of view, it is fully compatible with Intel® Pentium® 4 processors with Hyper-Threading3 (HT) Technology [6], and DP-based systems. However, special optimizations could be applied to improve the performance of the share-based cache organization.
• Each core has an independent thermal control unit (discussed later in this paper and also covered in [2]).
• The system combines per-core power state together with package-level power state.

The paper CMP Implementation in Intel® Core™ Duo Systems [1] extends the discussion on the CMP implementation and compares its performance with other configurations such as the use of split cache architecture. The results shown there indicate that the new proposed microarchitecture maximizes the performance benefits of both ST and MT execution at a given cache size. The enhancements we implemented in each of the cores allow us to improve both the ST performance (in specific cases) as well as the MT execution. It also allows us to improve the power and the thermal control of the system, and to achieve similar average power consumption, as was the case in the single-core Pentium® M processor.

Figure 3: The general structure of the Intel® Core™ Duo implementation
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