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Electronic Package Technology Development
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Electronic Package Technology Development
Volume 09    Issue 04    Published November 9, 2005
ISSN 1535-864X    DOI: 10.1535/itj.0904.03
  Section 1 of 8  
Nano and Micro Technology-Based Next-Generation Package-Level Cooling Solutions
Ravi S. Prasher, Technology and Manufacturing Group, Intel Corporation
Je-Young Chang, Technology and Manufacturing Group, Intel Corporation
Ioan Sauciuc, Technology and Manufacturing Group, Intel Corporation
Sridhar Narasimhan, Technology and Manufacturing Group, Intel Corporation
David Chau, Technology and Manufacturing Group, Intel Corporation
Greg Chrysler, Technology and Manufacturing Group, Intel Corporation
Alan Myers, Technology and Manufacturing Group, Intel Corporation
Suzana Prstic, Technology and Manufacturing Group, Intel Corporation
Chuan Hu, Technology and Manufacturing Group, Intel Corporation

Index words: microchannel, thermoelectric, thermal interface material, nanoparticles

Citation for this paper: Prasher, R. S.; Chang, J.-Y.; Sauciuc, I.; Narasimhan, S.; Chau, D.; Chrysler, G.; Myers, A.; Prstic, S.; Hu, C. "Nano and Micro Technology-Based Next Next-Generation Package-Level Cooling Solutions." Intel Technology Journal. http://developer.intel.com/technology/itj/2005/volume09issue04/
art03_nanoandmicro/p01_abstract.htm
(November 2005).
ABSTRACT

The design requirement for electronics cooling is to maintain the hottest location (hotspot) on the die (chip) below the specified temperature. Due to the presence of multiple hotspots, the thermal resistance near the die is very high. Total thermal resistance (Ψtot) can be written as:


click equation for larger view
(1)

where Rpackage, Rsi, RTIM1, and Rspreader are the thermal impedances of package, silicon, first-level Thermal Interface Material (TIM), and heat spreader, respectively. ΨTIM2 and Ψsink are the thermal resistances of second-level TIM and the heat sink, respectively, and Density Factor (DF) is a factor that accounts for the non-uniformity of heat generation. DF can possibly be greater than 1 if highly non-uniform power distribution exists or if the die size is very small. Since the thermal impedance near the die (Rpackage) gets multiplied by the DF, any reduction in the package impedance results in a larger reduction in Ψtot. Because of this reason, the focus of next-generation electronics cooling is on developing efficient cooling solutions near the package. Futuristic cooling solutions may be based on micro and nano technologies. These solutions might include a TIM made from micro and nanoparticles, a microchannel heat exchanger, and a Thin Film Thermoelectric Cooler (TFTEC) that is made of thin film superlattices, or nanocomposites, placed directly above the hotspots to provide localized cooling. In this paper, we focus on the technical merits of these technologies and discuss the challenges that must be met to make these technologies a reality for electronics cooling. The main challenges are: a) to reduce the boundary resistance between the nanoparticles and the host medium for nanoparticles-based TIMs and to increase the reliability performance of TIMs; b) reduce the assembly-related parasitic effects seen in TFTEC (for example, due to the very thin dimension of TFTEC, electrical contact resistance reduces the effective ZT in a package making it much smaller than the intrinsic ZT); and c) pumping requirements and pump reliability for microchannels. Water cannot be used as a coolant because the freezing requirements for electronics cooling is dictated by shipping and handling requirements and is much lower than 0°C. Traditional antifreeze liquids have much lower thermal conductivity and higher viscosity than water, forcing very severe pumping requirements in order to get the same thermal performance as water.

 

  Section 1 of 8  

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