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Intel Published Articles Published in or about Q3, 2003

  • Bailon, M.F.; Tarun, A.B.; Nery, M.; Munoz, J. Localization of Electrical Failures From The Backside of the Die: Failure Analysis Case Studies Using Infrared Emission Microscope. Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, July 2003. Pages: 193-197.
  • Barth, R. TRS Commodity Memory Roadmap. Records of the 2003 International Workshop on Memory Technology, Design and Testing, 2003, July 2003. Pages: 61-63.
  • Bhattacharya, Anandaroop; Sorrell, J. Mounting Of MEMS Pressure Sensors on Catheter Guide Wires Used in Balloon Angioplasty. Proceedings of SPIE, Volume 4958, Advanced Biomedical and Clinical Diagnostic Systems, July 2003. Pages: 235-241.
  • Bourianoff, G. The Future of Nanocomputing. Computer, Volume 36, Issue 8, August 2003. Pages: 44-53.
  • Bourianoff, George; Hutchby, James A.; Zhirnov, Victor; Cavin, Ralph. CMOS Devices and Beyond—A Process Integration Perspective. AIP Conference Proceedings, Volume 683, Issue 1, Sept 2003. Pages: 74-80.
  • Büyüksahin, Kavel M.; Patra, Priyadarsan; Naim, Farid N. ESTIMA: An Architectural-Level Power Estimator for Multi-Ported Pipelined Register Files. Proceedings of the 2003 International Symposium on Low Power Electronics and Design, Aug 2003. Pages: 294-297.
  • Castillo-Mejia, D.; Beaudoin, S. A Locally Relevant Wafer-Scale Model for CMP of Silicon Dioxide. Journal of the Electrochemical Society, Volume 150, Issue 9, Sept 2003. Pages: G581-6.
  • Chau, R.; Doyle, B.; Doczy, M.; Datta, S.; Hareland, S.; Jin, B.; Kavalieros, J.; Metz, M. Silicon Nano-Transistors and Breaking the 10nm Physical Gate Length Barrier. Device Research Conference, June 2003. Pages: 123-126.
  • Cheng, Wen-Hao; Chakravorty, Kishore K.; Farnsworth, Jeff N. Alternating Phase Shift Mask Architecture Scalability, Implementations, and Applications for 90-Nm And 65-nm Technology Nodes and Beyond. Proceedings of SPIE, Volume 5130, Photomask and Next-Generation Lithography Mask Technology X, August 2003. Pages: 766-777.
  • Clark, Lawrence T.; Choi, Byungwoo; Wilkerson, Michael. Reducing Translation Lookaside Buffer Active Power. Proceedings of the 2003 International Symposium On Low Power Electronics And Design, August 2003. Pages: 10-13.
  • Colwell, B. At Random - Engineering, Marketing Teams, and Management. Computer, Volume 36, Issue 9, Sept 2003. Pages: 5-7.
  • Concepcion, P.C.; Ramos, H.J. Hybrid Formation of TiCN Using Ion Beam Sputtering and Annealing Methods. The 30th International Conference on Plasma Science, 2003. IEEE Conference Record - Abstracts, June 2003. Pages: 416-416.
  • Conner, W. Steven; Chhabra, Jasmeet; Yarvis, Mark; Krishnamurthy, Lakshman. Experimental Evaluation of Synchronization and Topology Control for In-Building Sensor Network Applications. Proceedings of the 2nd ACM International Conference on Wireless Sensor Networks And Applications, Sept 2003. Pages: 38-49.
  • Constantinescu, C. Trends and Challenges In VLSI Circuit Reliability. IEEE Micro, Volume 23, Issue 4, July-Aug. 2003. Pages: 14-19.
  • Dam, Thuc H.; Pekny, Matt; Millino, Jim; Luu, Gibson; Melwani, Nitesh; Venkatramani, Aparna; Tavassoli, Malahat. SMIF Capability at Intel Mask Operation Improves Yield. Proceedings of SPIE, Volume 5130, Photomask and Next-Generation Lithography Mask Technology X, August 2003. Pages: 582-592.
  • Doyle, B.; Boyanov, B.; Datta, S.; Doczy, M.; Hareland, S.; Jin, B.; Kavalieros, J.; Linton, T.; Rios, R.; Chau, R. Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout. 2003 Symposium on VLSI Technology, Digest of Technical Papers, June 2003. Pages: 133-134.
  • Fall, Kevin. A Delay-Tolerant Network Architecture for Challenged Internets. Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications, August 2003. Pages: 27-34.
  • Fayneh, E.; Knoll, E. Clock Generation and Distribution for Intel Banias Mobile Microprocessor. Symposium on VLSI Circuits, Digest of Technical Papers, June 2003. Pages: 17-20.
  • Franca-Neto, L.M. High-Performance RF/microwave Integrated Circuits in Advanced Logic CMOS technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-Package. Proceedings of the 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sept 2003. Pages: 5-5.
  • Glasko, J.M.; Kvit, A.; Yankov, R. A.; Duscher, G.; Rozgonyi, G. Formation of Nanoscale Voids and Related Metallic Impurity Gettering in High-Energy Ion-Implanted and Annealed Epitaxial Silicon. Applied Physics Letters, Volume 83, Issue 7, August 2003. Pages: 1367-1369.
  • Gonzàlez, Antonio; Molina, Carlos; Aliagas, Carles; Garcia, Montse; Tubella, Jordi. Non Redundant Data Cache. Proceedings of the 2003 International Symposium on Low Power Electronics and Design, August 2003. Pages: 274-277.
  • Hady, F.T.; Bock, T.; Cabot, M.; Chu, J.; Meinecke, J.; Oliver, K.; Talarek, W. Platform Level Support for High Throughput Edge Applications: The Twin Cities Prototype. IEEE Network, Volume 17, Issue 4, July-Aug 2003. Pages: 22-27.
  • Hsu, S.; Chatterjee, B.; Sachdev, M.; Alvandpour, A.; Krishnmnurthy, R.K.; Borkar, S. A 90nm 6.5ghz 256x64b Dual Supply Register File with Split Decoder Scheme. 2003 Symposium on VLSI Circuits, Digest of Technical Papers, June 2003. Pages: 237-238.
  • Hsu, Steven; Borkar, Shekhar; Krishnamurthy, Ram; Chatterjee, Bhaskar; Sachdev, Manoj. Effectiveness and Scaling Trends of Leakage Control Techniques for Sub-130nm CMOS Technologies. Proceedings of the 2003 International Symposium on Low Power Electronics and Design, August 2003. Pages: 122-127.
  • Hussein, M.; Brain, R.; Turkot, R.; Jihpemg Leu; Singh, V.; Sivakumar, S.; Dual Damascene Patterning of Polymer Interlayer Dielectrics. Proceedings of the IEEE 2003 International Interconnect Technology Conference, June 2003. Pages: 33-35.
  • Jan, C.-H.; Bielefeld, J.; Buehler, M.; Chikamane, V.; Fischer, K.; Hepburn, T.; Jain, A.; Jeong, J.; Kielty, T.; Kock, S.; Marielb, T.; Miner, B.; Nguyen, P.; Schmitz, A.; Nashner, M.; Scherban, T.; Schroeder, B.; Wang, P.-H.; Wu, R. 90 nm Generation, 300mm Wafer Low K ILD/Cu Interconnect Technology. Proceedings of the IEEE 2003 International Interconnect Technology Conference, June 2003. Pages: 15-17.
  • Jensen, J.C.; Larson, L.E. A 16-GHz Ultra-High-Speed Si-Sige HBT Comparator. IEEE Journal of Solid-State Circuits, Volume 38, Issue 9, Sept 2003. Pages: 1584-1589.
  • Jiao, D.; Mazumder, M.; Chakravarty, S.; Dai, C.; Kobrinsky, M.J.; Harmes, M.C.; List, S. A Novel Technique for Full-Wave Modeling of Large-Scale Three-Dimensional High-Speed On/Off-Chip Interconnect Structures. International Conference on Simulation of Semiconductor Processes and Devices, (SISPAD), Sept 2003. Pages: 39-42.
  • Kam Meng Chong; Hang Keang Lim; Chin Seng Ong. Flip Chip Silicon Fracture Mechanism sith 3-Point Bend Metrology on Flip Chip Ball Grid Array. Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, July 2003. Pages: 97-102
  • Kee Sup Kim; Mitra, S.; Ryan, P.G. Delay Defect Characteristics and Testing Strategies. IEEE Design & Test of Computers, Volume 20, Issue 5, Sept-Oct 2003. Pages: 8-16.
  • Leu, Jihperng; Zhou, Ying; Xu, Guanghai; Scherban, Tracey; Kloster, Grant; Wu, Chih-I. Correlation of Surface and Film Chemistry with Mechanical Properties in Interconnects. AIP Conference Proceedings, Volume 683, Issue 1, Sept 2003. Pages: 455-461.
  • Lienhart, R.; Luhong Liang; Kuranov, A. A Detector Tree of Boosted Classifiers for Real-Time Object Detection and Tracking. Proceedings of the 2003 International Conference on Multimedia and Expo, ICME '03, Volume: 2, July 2003. Pages: 277-280.
  • Lin, W. A Multiple-Terminal Gate Charging Model. IEEE Electron Device Letters, Volume 24, Issue 8, Aug 2003. Pages: 521-523.
  • Lin, W.; Sery, G. Multiple-Terminal Gate Charging Effect - Competing/Compensating Charging Behavior. IEEE Electron Device Letters, Volume 24, Issue 7, July 2003. Pages: 481-483.
  • Matthew Ma; Gunther, S.H.; Greiner, B.; Wolff, N.; Deutschle, C.; Arabi, T.; Enhanced Thermal Management for Future Processors. 2003 Symposium on VLSI Circuits, Digest of Technical Papers, June 2003. Pages: 20-204.
  • Molinov, Sergey; Grzeszczuk, Radek; Hillesland, Karl E. Nonlinear Optimization Framework for Image-Based Modeling on Programmable Graphics Hardware. ACM Transactions on Graphics (TOG), Volume 22, Issue 3, July 2003. Pages: 925-934.
  • Muhtaroglu, A.; Taylor, G.; Rahal-Arabi, T.; Callahan, K. On-Die Droop Detector for Analog Sensing of Power Supply Noise. 2003 Symposium on VLSI Circuits, Digest of Technical Papers, June 2003. Pages: 193-196.
  • Munir, Saghir; Bald, Dan; Tolani, Vikram; Ghadiali, Firoz. DIVAS: An Integrated Networked System for Mask Defect Dispositioning and Defect Management. Proceedings of SPIE, Volume 5043, Cost and Performance in Integrated Circuit Creation, June 2003. Pages: 114-122.
  • Neogi, R.; Lee, K.; Panesar, K.; Zhou, J. Design and performance of a network-processor-based intelligent DSLAM. IEEE Network, Volume 17, Issue 4, July-Aug 2003. Pages: 56-62.
  • Pitzel, Steve. An Animator at Intel. ACM SIGGRAPH Computer Graphics, Volume 37, Issue 3, Aug 2003. Pages: 18-19.
  • Prasher, R. Generalized Equation of Phonon Radiative Transport. Applied Physics Letters, Volume 83, Issue 1, July 2003. Pages: 48-50.
  • Prasher, Ravi S. A Simplified Conduction Based Modeling Scheme for Design Sensitivity Study of Thermal Solution Utilizing Heat Pipe and Vapor Chamber Technology. Journal of Electronic Packaging, Volume 125, Issue 3, Sept 2003. Pages: 378-385.
  • Prasher, Ravi S.; Koning, Paul; Shipley, James; Devpura, Amit. Dependence of Thermal Conductivity and Mechanical Rigidity of Particle-Laden Polymeric Thermal Interface Material on Particle Volume Fraction. Journal of Electronic Packaging, Volume 125, Issue 3, Sept 2003. Pages: 386-391.
  • Qinghua Li; Rusch, L.A. Hybrid RAKE / Multiuser Receivers for UWB. Proceedings of the Radio and Wireless Conference, RAWCON '03, Aug 2003. Pages: 203-206.
  • Ratnasamy, S.; Gummadi, K.; Gummadi, R.; Gribble, S.; Shenker, S.; Stoica, I. The Impact of DHT Routing Geometry on Resilience and Proximity. Proceedings Of The 2003 Conference On Applications, Technologies, Architectures, and Protocols for Computer Communications, August 2003. Pages: 381-394.
  • Ratnasamy, Sylvia; Chawathe, Yatin; Breslau, Lee; Lanham, Nick; Shenker, Scott. Making Gnutella-Like P2P Systems Scalable. Proceedings of the 2003 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications, August 2003. Pages: 407-418.
  • Ratnasamy, Sylvia; Karp, Brad; Shenker, Scott; Estrin, Deborah; Govindan, Ramesh; Yin, Li; Yu, Fang. Data-Centric Storage in Sensornets with GHT, a Geographic Hash Table. Mobile Networks and Applications, Volume 8, Issue 4, Aug 2003. Pages: 427-442.
  • Ravi, A.; Banerjee, G.; Bishop, R.E.; Bloechel, B.A.; Carley, L.R.; Soumyanath, K. 10 GHz, 2omw, Fast Locking, Adaptive Gain Plls with On-Chip Frequency Calibration for Agile Frequency Synthesis in a .18µm Digital CMOS Process. 2003 Symposium on VLSI Circuits, Digest of Technical Papers, June 2003. Pages: 181-184.
  • Ravi, A.; Soumyanath, K.; Bishop, R.E.; Bloechel, B.A.; CarIey, L.R. An Optimally Transformer Coupled, 5GHz Quadrature VCO in a 0.18µm Digital CMOS Process. 2003 Symposium on VLSI Circuits, Digest of Technical Papers, June 2003. Pages: 141-144.
  • Regnier, G.; Minturn, D.; McAlpine, G.; Saletore, V.; Foong, A. ETA: Experience with an Intel® Xeon® Processor as a Packet Processing Engine. Proceedings of the 11th Symposium on High Performance Interconnects, Aug 2003. Pages: 76-82.
  • Satyanarayanan, M. Coping With Uncertainty. IEEE Pervasive Computing, Volume 2, Issue 3, July-Sept. 2003. Pages: 2-2.
  • Schilit, Bill N.; LaMarca, Anthony; Borriello, Gaetano; Griswold, William G.; McDonald, David; Lazowska, Edward; Balachandran, Anand; Hong, Jason; Iverson, Vaughn. Challenge: Ubiquitous Location-Aware Computing and the "Place Lab" Initiative. Proceedings of the 1st ACM International Workshop on Wireless Mobile Applications and Services on WLAN hotspots, Sept 2003. Pages: 29-35.
  • Silverman, Peter J.; Gwyn, Charles W. EUVL: Transition from Research to Commercialization. Proceedings of SPIE, Volume 5130, Photomask and Next-Generation Lithography Mask Technology X, August 2003. Pages: 990-1004.
  • Simmons, E. From Requirements to Release Criteria: Specifying, Monitoring, and Demonstrating Product Quality. Proceedings of the 11th IEEE International Requirements Engineering Conference, Sept. 2003. Pages: 286-286.
  • Song, J.; Jian Li; Yen-Kuang Chen. Quality-Delay-and-Computation Trade-Off Analysis of Acoustic Echo Cancellation on General-Purpose CPU. Proceedings of the 2003 International Conference on Multimedia and Expo, ICME '03, Volume 2, July 2003. Pages: 837-840.
  • Starikov, Alexander; Allgair, John A.; Boksha, Victor V.; Bunday, Benjamin D.; Diebold, Alain C.; Cole, Daniel C.; Davidson, Mark P.; Hutcheson, Jerry D.; Gurnell, Andrew W.; McIntosh, John M.; Muckenhirn, Sylvain G.; Pellegrini, Joseph C.; Larrabee, Robert D.; Potzick, James E.; Vladar, Andras E.; Smith, Nigel P.; Sullivan, Neal T.; Wells, Oliver C. Applications of Image Diagnostics to Metrology Quality Assurance and Process Control. Proceedings of SPIE, Volume 5042, Design and Process Integration for Microelectronic Manufacturing, July 2003. Pages: 251-277.
  • Stinson, J.; Rusu, S. A 1.5GHz third generation Intel® Itanium® 2 processor. Proceedings of the Design Automation Conference, June 2003. Pages: 706-709.
  • Sun, Peng; Ayre, Caroline; Wallace, Matthew. Characterization of Organic Contaminants Outgassed from Materials Used in Semiconductor Fabs/Processing. AIP Conference Proceedings, Volume 683, Issue 1, Sept 2003. Pages: 245-253.
  • Tam, S.; Desai, U.; Limaye, R. Clock Generation and Distribution for the Third Generation Itanium Processor. 2003 Symposium on VLSI Circuits, Digest of Technical Papers, June 2003. Pages: 9-12.
  • Tang, S.; Narendra, S.; De, Vivek. Temperature and Process Invariant MOS-Based Reference Current Generation Circuits for Sub-1V Operation. Proceedings of the 2003 International Symposium on Low Power Electronics and Design, Aug. 2003. Pages: 199-204.
  • Tarun, A.B.; Laniog, J.N.; Tan, J.; Cana, P. Junction Leakage Analysis Using Scanning Capacitance Microscopy. Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, July 2003. Pages: 213-216.
  • Zachariah, S.T.; Chakravarty, S. Algorithm to Extract Two-Node Bridges. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 11, Issue 4, Aug 2003. Pages: 741-744.
  • Zhang, Guojing; Naulleau, Patrick; Goldberg, Kenneth A.; Anderson, Erik H.; Bokor, Jeffrey; Gullikson, Eric; Harteneck, Bruce; Jackson, Keith; Olynick, Deirdre; Salmassi, Farhad; Baker, Sherry; Mirkarimi, Paul; Spiller, Eberhard; Walton, Chris. Lithographic Characterization of the Printability of Programmed Extreme Ultraviolet Substrate Defects. Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Volume 21, Issue 4, July 2003. Pages: 1286-1290.
  • Zhang, K.; Bhattacharya, U.; Ma, L.; Ng, Y.; Zheng, B.; Bohr, M.; Thompson, S. A Fully Synchronized, Pipelined, and Re-Configurable 50mb Sram on 90nm CMOS Technology for Logic Applications. 2003 Symposium on VLSI Circuits, Digest of Technical Papers, June 2003. Pages: 253-254.
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