65nm Silicon Technology

Intel® 65nm silicon technology roughly doubles transistor density compared to the previous 90nm generation, and delivers powerful performance and performance efficiency. Additional transistors provide the foundation to deliver advanced capabilities-from dual and quad-core design and increased cache, to innovative technologies such as virtualization and security enhancements that provide the foundation for energy-efficient, feature rich computing solutions.

65nm transistor technologies include:

• Second generation strained silicon with 10-15 percent improved drive current (over the 90nm process) for improved performance
• 1.2nm gate oxide and 35nm gates for improved performance
• NiSi for low resistance cap on gates and source-drains
• Lower interconnect capacitance through low-k carbon doped oxide dielectric and 0.7x line length scaling, providing increased performance and lower power

Delivering energy-efficiency

Energy-efficient performance begins with energy-efficient transistors. As transistors get smaller (a nanometer is one-billionth of a meter), more power and heat dissipation issues develop. As a result, implementing new features, techniques and structures is imperative to continuing microprocessor innovation. Intel has addressed these challenges by integrating power-saving features into the 65nm process technology. These features are critical to delivering energy-efficient performance across computing and communications products.

This second generation of Intel® strained silicon increases transistor performance by 10 to 15 percent without increasing leakage compared to the first generation in 90nm silicon technology. Conversely, these transistors can cut leakage by four times at constant performance compared to 90nm transistors.¹

Intel's 65nm transistors have a reduced gate length of 35 nanometers and a gate oxide thickness of 1.2 nanometers, which combine to provide improved performance and reduced gate capacitance.

The reduced gate capacitance ultimately lowers a chip's active power. The new process also integrates eight copper interconnect layers (see photo), and uses a "low-k" dielectric material that increases the signal speed inside the chip and reduces chip power consumption. "Sleep transistors" have also been implemented in the 65nm SRAM. Sleep transistors shut off the current flow to large blocks of the SRAM when they are not being utilized, eliminating a significant source of power consumption on a chip. This feature is especially beneficial for battery-powered devices, like laptops.

Technical papers

An advanced low power, high performance, strained channel 65nm technology

• Download the white paper (PDF 487KB)

A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57µm² SRAM Cell

• Download the white paper (PDF 1.2MB)
• View the presentation (PDF 1.24MB)

Tick Tock-the beat goes on with 45nm and 32nm

Intel® 45nm high-k (Hi-k) metal gate silicon technology extends Intel's record of ramping production on a new process generation every two years and demonstrates the ability to continue delivering the benefits of Moore's Law. Using dramatically new materials including hafnium, the new Intel® 45nm Hi-k metal gate silicon technology is one of the biggest breakthroughs in fundamental transistor design in 40 years. Beyond Intel® 45nm Hi-k silicon technology, look for Intel's upcoming 32nm silicon process technology in 2009.

• Get more on Intel® silicon technology and manufacturing
• Intel® 45nm Hi-k metal gate silicon technology
• Intel demonstrates first 32nm chip