What is multi-core architecture?

Explained most simply, a dual-core processor entails silicon design engineers placing two Intel® Pentium® "execution cores," or computational engines, within a single processor. This dual-core processor plugs directly into a single processor socket, but the operating system perceives each of its execution cores as a discrete logical processor, with all the associated execution resources. Future versions of Intel’s multi-core architecture processors will have more than two execution cores.

For additional questions about on multi-core processors, please refer to the following documentation: http://www.intel.com/cd/ids/developer/asmo-na/eng/dc/pentium4/221188.htm


What is the difference between multi-core architecture and Hyper-Threading (HTTechnology) Technology?

HT Technology is limited to a single core using existing execution resources more  efficiently to better enable threading, whereas multi-core capability provides two complete sets of execution resources to increase compute throughput. Any application that has been threaded for HT Technology should deliver great performance when run on an Intel multicore processor-based system. Accordingly, users will be able to take advantage of many existing applications that are already optimized for two threads from the earliest days of Intel’s transition to multi-core architectures across its desktop, mobile and server processor product lines.


Will my application work on a multi-core system if my code is not threaded?

Intel’s tradition of backwards compatibility goes back to its earliest processors and continues today. Any application that will run on a single core Intel processor will run on an Intel multi-core processor. However, in order for an application to take advantage of the multi-core capabilities, the code should be multithreaded.


What applications are good candidates to be moved from serial to multi threaded to experience performance gains on multi-core systems?

First, any program that is in a class of applications where threading is already relatively common – video encoding, 3D rendering, video/photo editing and high performance computing/workstation applications. These applications are especially amenable to thread level parallelism because many of their computations can run simultaneously. Second,though most games are single-threaded today, gaming applications also can benefit from multithreading. For example, physics and artificial intelligence (AI) can run on separate threads, potentially leading to a more realistic and challenging gaming environment. Finally,Intel has plans to quickly transition to multi-core architecture across all of its product lines and most industry watchers expect processor clock speeds to level off in the years ahead.The implication is that, in the near future, threading and concurrency will be increasingly important in boosting the performance of all software.


Besides using threaded applications, when else might end users experience a performance gain on multi-core systems?

Multitasking users or those working in environments marked by lots of background processing also should benefit from multi-core systems. Behind-the-scenes processing is increasingly the norm in business computing environments. Examples include users who run background data mining queries while working on other tasks in the foreground or corporate IT departments that unobtrusively update software, troubleshoot hardware or perform virus scanning and other management tasks over the corporate network.


How do the Intel® Core™2 Duo processors, Intel® Core™2 Solo processors, Intel® Core™ Duo processors, Intel® Core™ Solo processors, Intel® Celeron® M processors, and Intel® Pentium® M processors differ from each other?

The Intel® Core™2 Duo processor includes up to 4MB of shared L2 cache, up to 1333 MHz front side bus for desktop, and up to 800 MHz front side bus for laptop. The Intel® Core™2 Duo processor supports Intel® Wide Dynamic Execution, Intel® Intelligent Power Capability, Intel® Smart Memory Access, Intel® Advanced Smart Cache, and Intel® Advanced Digital Media Boost.

The Intel® Core™2 Solo processor is the next generation mobile processor for power-optimized mobile processing. It is enhanced to handle today's demanding software applications such as CAD tools, 3D and 2D modeling or serious number-crunching programs.

The Intel® Core™ Duo processor is the next-generation processor in the latest Intel® Centrino® mobile technology-based notebooks and delivers revolutionary dual-core mobile performance and great power efficiency.

The Intel® Core™ Solo processor represents the next generation in processor innovation. It is enhanced to handle today's demanding software applications—such as graphics-intensive games or serious number-crunching programs.

The Intel® Pentium® M processor is designed, tested and tuned for mobility, including breakthrough mobile performance, enabling great battery life, enabling sleeker, lighter laptop designs.

The Intel® Celeron® M processor delivers a balanced level of mobile processor technologies mobile performance, lower voltage enables sleeker, lighter laptop designs at an exceptional value.

For more information see the processor comparison table and the Intel® Centrino® Processor Technology product comparison chart.


What is Micro-Ops Fusion?

Micro-Ops Fusion is a technology that uses fewer CPU resources to execute operations than traditional microprocessors by merging CPU operations together prior to execution in order to increase performance and efficiency. When the micro-operations are fused they use less processor resources in order to handle the same number of operations. Two fused micro-operations occupy a single resource and thus they make the machine behave as a wider machine. Micro-ops fusion delivers efficiency in both performance and power management.

Analogy: A taxi pooling multiple riders into a single trip to save time and energy.


What is Advanced Instruction Prediction?

Advanced instruction prediction is a technology that allows the processor to study the past behavior of programs and intelligently anticipate what instructions will be needed next. The processor can line up instructions for execution before a program requests them. By anticipating changes in program flow rather than merely responding to them, the processor improves performance and efficiency. Predicting branches correctly is one of the areas of high leverage for both performance and power. On top of the standard Bi-Model/Global predictor the processor also includes a loop detector and an indirect branch target buffer.

Analogy: A word processing program that completes a word after you type the first few letters, improving speed and efficiency.


What is the dedicated stack manager?

The dedicated stack manager significantly reduces the number of micro-operations required for the "overhead" of stack management inside the processor. Traditional processors repeatedly interrupt program execution to maintain their own internal accounting. Processors with a dedicated stack manager use sophisticated, specialized hardware enabling the processor to execute program instructions without interruption, using less power.

Certain instructions use the architectural stack as source of operands. In those instructions there's an overhead work of managing the stack on top of the actual operation that needs to occur. Typically those overhead operations are done using the main machine flow which is a very inefficient way from both power and performance perspective. There are advanced synchronization mechanisms that make sure that the stack pointer value is visible to the software just when it's needed.


What is the power-optimized processor system bus?

The power-optimized processor system bus remains powered down until it senses incoming data form the chipset, allowing to the processor to consume less power. In a typical microarchitecture, a processor has its bus turned on even when it is not in use. With the Pentium M processor and Celeron M processor, portions of the bus are turned on only when they are needed. Architectural and circuit innovations enabled this power-optimized processor system bus technology which lowers power through reduced voltage swing and tighter buffer management.


What is intelligent power distribution?

Most machines employ some level of hardware clock gating to reduce power consumption. Pentium M processor and Celeron M processor implements finer granularity hardware gating mechanisms that allows turning on hardware units partially based on program demand.

Analogy: A motion sensor that turns lights on when you enter a room and shuts them off when you exit.


What is the large, power-aware Secondary Cache?

The Pentium M processor includes a 1MB or 2MB secondary cache and Celeron M processor includes 512K or 1MB secondary cache. The large cache allows a significant reduction in memory data latency providing a big performance improvement. The power-aware cache implements several features to reduce cache power consumption. Traditional microprocessors run the cache as fast as possible, the processor cache on the processor runs slightly slower to save energy and cut down on electricity leakage enabling longer battery life. Special circuit and micro-architectural innovations were implemented in order to reduce power consumption. For example the cache unit keeps track of the last entry that was accessed such that repeating accesses to the same location will not have to lookup the array, thus eliminating a high power operation.


What is deeper sleep alert state?

Deep Sleep and Deeper Sleep Alert States are very low power states the processor can enter during periods of inactivity while still maintaining its context. The Deeper Sleep Alert State is functionally identical to the Deep Sleep Alert State but at a significantly lower voltage providing added benefits of power savings and longer battery life. The Deeper Sleep Alert State is automatically enabled on the platform through the I/O Controller Hub component and the voltage regulator, so there is no user interaction required. This feature maintains processor performance characteristics while taking advantage of the increased power savings.


Explain mobile packaging technology.

Flip-chip packaging eliminated the wire-bond approach in favor of mounting the die directly to a substrate, improving power delivery and reducing impedance.

The mobile Micro-FCPGA (micro flip chip pin grid array) and Micro-FCBGA (micro flip chip ball grid array) packaging technology provides significant improvements in power delivery and pin inductance compared to their predecessors resulting in dramatically improved performance. The packages incorporate separate power and ground planes and on-package capacitance needed at higher speeds - reducing board space for the implementation. Space savings contribute to smaller designs and more mobility.


What is streaming SIMD extensions 2 (SSE2)?

The microarchitecture includes the new extensions to SIMD capabilities that MMX™ technology and SSE technology delivered by adding 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase. They accelerate a broad range of applications, including video, speech, and image, photo processing, encryption, financial, engineering and scientific applications.


What is an S-Spec Number?

An S-Spec number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.).

This applies to:

Intel® Core™2 Solo Processor