Under certain conditions, Intel® validation teams have observed marginal signal quality on certain strobe signals, DQS_x[17:0], in the registered DDR 266 memory interface of the above listed server board products. Poor signal quality on the DQS signals will result in the MCH DDR read FIFO getting out of sync during memory READ transactions leading to single-bit or multi-bit errors on the DQ_x[63:0] signals. Depending on the system configuration, the system may hang and/or a system NMI should be generated.

	TA_639 [PDF]
	File Name: ta_639.pdf Size: 126484 bytes Date: 3/20/2003

This applies to:

Intel® Server Board SE7501HG2 Intel® Server Board SE7501WV2