Intel® E7525 ChipsetOverview
Intel® E7525 Memory Controller Hub (MCH) chipset, the next generation Intel® dual-processor (DP) workstation and server chipset technology, offers increased graphics performance, reduced power consumption, and improved platform reliability and system manageability. These new dual-processor workstations deliver outstanding performance, dependability and value to digital content creation, Mechanical Computer Aided Design (MCAD), electronic design automation, and other graphics workstation applications.
Features and benefits
|Supports 2 Intel® Xeon® processors over an 800 MHz system bus for dual-processing workstation and server systems||Optimized performance for the DP workstation market segment with a range of price points.|
|800 MHz system bus capability||Increased bus bandwidth (50% greater than 533 MHz) and increased system bandwidth.|
|PCI Express*1 4 X-16 graphics||Next generation graphics interface, delivers 4.0 GB/s of graphics bandwidth per direction directly into the Intel® E7525 MCH chipset (total bandwidth 8 GB/s), for twice the bandwidth of AGP 8X.|
|PCI Express* I/O||Serial I/O technology provides a direct connection between the MCH chipset and PCI Express* component/adapters with bandwidth up to 4 GB/s on each PCI Express x8 interface. PCI Express offers higher bandwidth, lower latency and fewer I/O bottlenecks than PCI-X.|
|Intel® 6700PXH 64-bit PCI Hub||
|Advanced platform RAS||
|Intel® Hub Interface 1.5 connection to the MCH chipset||Point-to-point connection between the MCH chipset and the Intel® 82801ER I/O controller hub or Intel® 6300ESB I/O controller hub devices provides 266 MB/s of bandwidth.|
|Chipsets||Intel® E7520 and E7320 Chipsets|
|Intel® E7525 Memory Controller Hub (MCH) chipset||1077 Flip Chip-Ball Grid Array (FC-BGA)|
|Intel® 6700PXH 64-bit PCI Hub||567 Flip Chip-Ball Grid Array (FC-BGA)|
|Intel® 82801ER (ICH5R)||460 Micro Ball Grid Array (µBGA)|
|Intel® 6300ESB I/O Controller Hub||689 Plastic Ball Grid Array (PBGA)|
1 PCI Express* reduced power-state "L0s" is not supported.
2 In an x4 DDR memory device, the Intel® x4 Single Device Data Correction (x4 SDDC) provides error detection and correction for 1, 2, 3 or 4 data bits within that single device and provides error detection, up to 8 data bits, within two devices.