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Intel® 5100 Memory Controller Hub Chipset for Embedded Computing Supporting Intel® Core™2 Duo processors SL9400 and T9400

  • Overview
  • Technical Documents

The power-optimized Intel® 5100 Memory Controller Hub Chipset (Intel® 5100 MCH Chipset) supports development with the energy-efficient 45nm Intel® Core™2 Duo processor T9400, providing a compelling performance-per-watt advantage for single-processor bladed form factor applications. Chipset power savings are derived from lower thermal design power (TDP) in the MCH, a low-power Intel® 82801IR I/O Controller Hub 9R (ICH9R), and standard native DDR2 memory technology.

The Intel® Core™2 Duo processor SL9400 has a 1.86 GHz core speed, 1066 MHz front-side bus (FSB) and 17 watts TDP in a 956-ball FC-BGA package. The Intel Core 2 Duo processor T9400 has a 2.53 GHz core speed, 1066 MHz Front-Side Bus (FSB), 35 watt TDP, and offers two package options—479 μFC-BGA and 478 μFC-PGA. This Intel 5100 MCH chipset-based platform provides 30 lanes of PCI Express* (PCIe*) for I/O connectivity and supports dual-channel DDR2 registered ECC memory to help safeguard data and improve reliability.

This platform addresses the high-performance, low-power needs of single-processor bladed form factors in security, voice, wireless infrastructure and embedded market segments. It is ideal for a wide range of applications, such as routers, IP-PBX, converged/unified communications platforms, content firewalls and unified threat management (UTM) systems.

Product information

Features and benefits

Native DDR2 Registered DIMM technology
  • Six slots supporting configurable low power DDR2 memory, with a maximum capacity of 48 GB.
  • Fast speed memory operating at 533/667 MHz.
  • Registered ECC DIMMs help protect data and improve reliability.
Intel® Virtualization Technology (Intel® VT)¹ A processor hardware enhancement that assists virtualization software to deliver more efficient virtualization solutions and greater capabilities, including 64-bit guest OS support.
PCI Express*
  • The Intel® 5100 MCH chipset supports six x4 PCIe* links. Each x4 link may be combined into three x8 links or one x16 link for configuration flexibility.
  • The Intel® ICH9R supports six x1 lanes that can be combined into one x4 and two x1 links, or six x1 links.
Memory Reliability, Accessibility and Serviceability (RAS) features
  • Demand and patrol scrubbing proactively searches system memory, repairing correctable errors for enhanced system reliability.
  • Optional memory sparing swaps defective DIMMs with installed but otherwise unused DIMMs for improved availability.
  • x4 Single Device Data Correction (SDDC) can repair a failed x4 DRAM device on-the-fly, utilizing advanced ECC capabilities.
  • Error correcting code corrects single-bit and detects double-bit errors.

Packaging information

Product Package
Intel® 5100 Memory Controller Hub Chipsets 1432 Flip Chip-Ball Grid Array (FC-BGA)
Intel® 82801IR I/O Controller Hub (ICH-9R) 676 Flip Chip - Ball Grid Array (FC-mBGA)

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