Intel® 5000V ChipsetOverview
Intel's new server chipsets for the Dual-Core Intel® Xeon® processor 5000 series enable Intel® dual-processor (DP) balanced server platforms that are efficient, dependable, and responsive.
Intel® dual-core processor-based platforms help businesses better utilize assets with effective virtualization and increase density in their data centers through optimized power and thermal features.
The new dual-core processor servers offer increased value to enterprise front-end, small to medium business (SMB), and high-performance computing (HPC) applications.
Product information
- Server Chipset Comparison chart
-
Download product brief
File Type/Size: PDF 168KB
){kind=link}
Features and benefits
| Supports two Dual-Core Intel® Xeon® processors 5000Δ series | Optimized performance for the DP Server market segment with a range of price points. |
|---|---|
| 1066 / 13331 MHz dual independent buses | Increased bus bandwidth of up to 3X over 800 MHz systems. |
| FB DIMM 533/667 MHz memory interface | Offers a maximum memory bandwidth up to 8.5 GB/s for 533 MHz and 10.5 GB/s for 667 MHz. Increased dual in-line memory modules (DIMMs) per system provide enhanced memory scalability for memory-intensive applications. |
| PCI Express*2 I/O | Serial I/O technology provides a direct connection between the MCH chipset and PCI Express* component/adapters with bandwidth up to 4 GB/s on each PCI Express x8 interface. PCI Express offers higher bandwidth, lower latency and fewer I/O bottlenecks than PCI-X. |
|
Intel® 6700PXH 64-bit PCI Hub
The Intel® 6700PXH 64-bit PCI Hub is targeted for the server market. It is a peripheral component that performs PCI bridging functions between the PCI Express* interface and the PCI Bus. It contains two PCI bus interfaces that can be independently configured to operate in PCI (33 or 66 MHz) or PCI-X Mode 1 (66, 100, or 133 MHz), for either 32 or 64 bit PCI devices. It further supports the new PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0. File Type/Size: PDF 2271KB | Optional component introduces next-generation PCI/PCI-X performance and significant enhancements to platform flexibility. Supports two independent 64-bit, 133 MHz PCI-X segments and two Hot-Plug controllers (one per segment). |
|
Advanced platform reliability, availability, and serviceability (RAS)
File Type/Size: PDF 148KB | Features such as memory Error Correction Code (ECC), Intel® x4 Single Device Data Correction (x4 SDDC),3 DIMM sparing and DIMM scrubbing for improved system reliability. The System Management Bus (SMBus) hooks into the Intel® 5000V MCH chipset for remote management operation and support for a variety of third-party base management controller (BMC) and BIOS solutions. |
Related products
| Processors | |
|---|---|
| Chipsets | |
| Server boards |
Packaging information
| Intel® 5000V Memory Controller Hub (MCH) chipset | 1432 Flip Chip-Ball Grid Array (FC-BGA) |
|---|---|
|
Intel® 6700PXH 64-bit PCI Hub
The Intel® 6700PXH 64-bit PCI Hub is targeted for the server market. It is a peripheral component that performs PCI bridging functions between the PCI Express* interface and the PCI Bus. It contains two PCI bus interfaces that can be independently configured to operate in PCI (33 or 66 MHz) or PCI-X Mode 1 (66, 100, or 133 MHz), for either 32 or 64 bit PCI devices. It further supports the new PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0. File Type/Size: PDF 2271KB | 567 Flip Chip-Ball Grid Array (FC-BGA) |
| Intel® 6321ESB I/O Controller Hub | 1284 Flip Chip - Ball Grid Array (FC-BGA) |
Δ Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number/ for details.
1The 1333 MHz system bus feature will be available in the second half of 2006.
2PCI Express* reduced power-state "L0s" is not supported.
3In an x4 DDR memory device, the Intel® x4 Single Device Data Correction (x4 SDDC) provides error detection and correction for 1, 2, 3 or 4 data bits within that single device and provides error detection, up to 8 data bits, within two devices.