Intel® 5000P ChipsetOverview
Intel's new server chipsets for the Dual-Core Intel® Xeon® processor 5000 series enable Intel® dual-processor (DP) balanced server platforms that are efficient, dependable, and responsive.
Intel® dual-core processor-based platforms help businesses better utilize assets with effective virtualization and increase density in their data centers through optimized power and thermal features.
With the Intel 5000P or Intel 5000V chipset and Dual-Core Intel Xeon processor 5000 series, system designers can offer new platforms that help IT services move ahead with increased productivity, higher throughput, and faster time-to-solution.
The Intel® 5000P chipset, the next generation Intel® dual-processor (DP) server chipset technology, offers increased graphics performance, reduced power consumption, and improved platform reliability and system manageability.
Product information
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Features and benefits
| Supports two Dual-Core Intel® Xeon® processors 5000Δ series | Optimized performance for intensive computing demands of enterprise and small to medium business servers, plus high performance computing applications. |
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| 1066 / 13331 MHz dual independent buses | Increased bus bandwidth of up to 3X over 800 MHz systems. |
| FB DIMM 533/667 MHz memory interface | Offers a maximum memory bandwidth up to 17 GB/s for 533 MHz and 21 GB/s for 667 MHz. Increased dual in-line memory modules (DIMMs) per system, providing enhanced memory scalability for memory-intensive applications. Up to 64 GB memory capacity. |
| PCI Express*2 I/O | Serial I/O technology provides a direct connection between the MCH and PCI Express components/adapters, with bandwidth up to 4 GB/s on each PCI Express x8 interface. |
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Intel® 6700PXH 64-bit PCI Hub
The Intel® 6700PXH 64-bit PCI Hub is targeted for the server market. It is a peripheral component that performs PCI bridging functions between the PCI Express* interface and the PCI Bus. It contains two PCI bus interfaces that can be independently configured to operate in PCI (33 or 66 MHz) or PCI-X Mode 1 (66, 100, or 133 MHz), for either 32 or 64 bit PCI devices. It further supports the new PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0. File Type/Size: PDF 2271KB | Optional component introduces next-generation PCI/PCI-X performance and significant enhancements to platform flexibility. Supports two independent 64-bit, 133 MHz PCI-X segments and two Hot-Plug controllers (one per segment). |
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Advanced platform reliability, availability, and serviceability (RAS)
File Type/Size: PDF 148KB | Features such as memory Error Correction Code (ECC), Intel® x4 Single Device Data Correction (x4 SDDC), DIMM sparing and DIMM scrubbing for improved system reliability. The System Management Bus (SMBus) port hooks into the Intel® 5000P MCH chipset for remote management operation and support for a variety of third-party base management controller (BMC) and BIOS solutions. |
Related products
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| Chipsets | |
| Server boards |
Packaging information
| Intel® 5000P Memory Controller Hub (MCH) chipset | 1432 Flip Chip-Ball Grid Array (FC-BGA) |
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Intel® 6700PXH 64-bit PCI Hub
The Intel® 6700PXH 64-bit PCI Hub is targeted for the server market. It is a peripheral component that performs PCI bridging functions between the PCI Express* interface and the PCI Bus. It contains two PCI bus interfaces that can be independently configured to operate in PCI (33 or 66 MHz) or PCI-X Mode 1 (66, 100, or 133 MHz), for either 32 or 64 bit PCI devices. It further supports the new PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0. File Type/Size: PDF 2271KB | 567 Flip Chip-Ball Grid Array (FC-BGA) |
| Intel® 6321ESB I/O Controller Hub | 1284 Flip Chip - Ball Grid Array (PBGA) |
Δ Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number/ for details.
1The 1333 MHz system bus feature will be available in the second half of 2006.
2PCI Express* reduced power-state "L0s" is not supported.