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Shiuh-Wuu Lee
Intel Fellow, Technology and Manufacturing Group
Director, Advanced Circuit Simulation Computer-Aided Design
INTEL CORPORATION
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 | S.W. Lee, "Modeling for Pre-Silicon Design Verification", invited paper, Fourth Workshop on Compact Modeling, Nanotech 2005 (Anaheim)), May 2005. |
| S.W. Lee, "Emerging challenges in TCAD for product design in the coming decade", invited speakers, 7th International Conference on Solid-State and Integrated-Circuit Technology (Beijing, China), October 2004. |
| D. Jiao, C. Dai. S.W. Lee, T. Arabi and G. Taylor, "Computational electromagnetics for high-frequency IC design," IEEE International Symposium on Antennas and Propagation (Monterey, CA), pp. 3317-3320, June 2004. |
| S.W. Lee, "Technology evolution and the emerging challenges in modeling for product design," keynote speaker, Workshop on Recent Advances in Microprocessor and Communication Design Technology (IEEE Components, Packaging and Manufacturing Technology Society, Oregon Chapter), April 2004. |
| S.W. Lee, "Roles and Requirements of Compact Model in Technology Development, Product Design, and Manufacturing," invited speaker, Third Workshop on Compact Modeling, Nanotech 2004 (Boston), March 2004. |
| S.W. Lee, "Physical Compact Modeling," invited speaker, Sixth International Conference on Modeling and Simulation of Microsystems (San Francisco), March 2003. |
| S.W. Lee, "Integrated TCAD and ECAD solutions - a paradigm shift," invited plenary session speaker, International Conference on Simulation of Semiconductor Processes and Devices (Kobe, Japan), pp. 5-8, 2002. |
| C. Dai, N. Hakim, S. Walstra, S. Hareland, J. Maiz, S. Yu and S.W. Lee, "Neutron-SER modeling and simulation for 0.18 um CMOS technology," International Conference on Simulation of Semiconductor Processes and Device (Athens, Greece), pp. 278-283, 2001. |
| C. Dai, N. Hakim , S. Hareland, W. Kang, P. Karhade , D. Kranowski , N. Husain , S.W. Lee, J. Maiz, H. M. Nguyen, S. V. Walstra and Y. Yagil , "FUB SER simulation methodologies, models, and tools," Design and Testing Technology Conference (San Francisco), 1999. |
| C. Dai, N. Hakim, S. Hareland, J. Maiz and S.W. Lee, "Alpha-SER modeling & simulation for sub-0.25?m CMOS technology," Symposium on VLSI Technology (Kyoto, Japan), 1999. |
| N. Husain, A. Efrati, W. Kang, S.W. Lee, P. Li, D. Song and Y. Yagil, "RV technology trend and program," Design and Testing Technology Conference (Portland, Oregon), 1998. |
| C. Dai, S. Walstra and S.W. Lee, "The effect of intrinsic capacitance degradation on circuit performance," Symposium on VLSI Technology (Hawaii), pp. 196-197, 1996. |
| S.W. Lee, "Status and Future Direction in Compact Device Modeling," Custom Integrated Circuit Conference, invited speaker (Santa Clara), 1996. |
| S.W. Lee, "Requirements of Industry-Standard Compact Model," invited speaker, Sematech Compact Model Workshop (Austin, TX), 1995. |
| S.W. Lee, "A capacitance-based method for experimental determination of metallurgical channel length of submicron LDD MOSFET's," IEEE Trans. Electron Devices, vol. 41, pp. 403-412, 1994. |
| S.W. Lee, "Characterization of metallurgical channel length and gate electrode's physical dimension for device analysis and calibration of numerical device and process simulator," International Workshop on VLSI Process and Device Modeling (Nara, Japan), pp. 112-113, 1993. |
| S. W. Lee, "A proposed method for determining MOSFET gate electrode's bottom dimension and the on-state fringing capacitance," IEEE Trans. Computer Aided Design, vol. CAD-12, no. 1, 1993. |
| S. W. Lee, C. L. Liang, C. S. Pan, W. Lin and J. B. Mark, "A study on the physical mechanism in the recovery of gate capacitance to Cox in implanted polysilicon MOS structures," IEEE Electron Device Lett., vol. 13, pp. 2-4, 1992. |
| A. T. Wu, S. W. Lee, T. Y. Chan and V. Murali, "Temperature and field dependence of carrier mobility in MOSFETs with reoxidized nitrided oxide gate dielectrics," Solid-State Electronics, vol. 35, pp. 27-32, 1992. |
| T. Dang, S. W. Lee and S. P. Joshi, "Characterization and calibration of PISCES mobility and hot carrier models for predictive device simulation," Device Workshop (Mt. Hood, Oregon), October 1991. |
| L. C. Chien and S. W. Lee, "SUPREM3 characterization and physical modeling of the anomalous C-V and I-V characteristics of MOSFETs with arsenic implanted polysilicon gate," Device Workshop (Mt. Hood, Oregon), October, 1991. |
| S. W. Lee and J. Garcia-Colevatti, "A non-destructive method for direct determination of the effective dimension and fringing capacitance of deep submicron MOSFET's gate electrode," Device Workshop (Mt. Hood, Oregon), October 1991. |
| S. W. Lee, S. Hu, J. Mark and B. Asakawa, "Calibration and application of two-dimensional device simulator PISCES for polysilicon emitter bipolar transistor modeling," Device Workshop (Mt. Hood, Oregon), October 1991. |
| S. W. Lee, "Electrical characterization of the effective dimension and fringing capacitance of MOSFET's gate electrode," Intel Technology Journal, summer issue, pp. 12-18, 1991. |
| A. T. Wu, S. W. Lee, V. Murali and M. Garner, "Off-state gate current in n-channel MOSFETs with nitrided oxide gate dielectrics," IEEE Electron Device Lett., vol. 11, pp. 499-501, 1990. |
| S. W. Lee and T. Y. Chan, "A closed-loop evaluation and validation of a method for determining the scattering limited carrier velocity in MOSFETs," IEEE Trans. Electron Devices, vol. 37, pp. 2388-2394, 1990. |
| T. Y. Chan, S. W. Lee and H. Gaw, "Experimental characterization and modeling of electron saturation velocity in MOSFET's inversion layer from 90 to 350 K," IEEE Electron Device Lett., vol. 11, pp. 466-468, 1990. |
| S. W. Lee, "Extraction of MOSFET carrier mobility characteristics and calibration of a mobility model for numerical device simulation," Solid-State Electronics (Special Issue on Material and Process Characterization for Semiconductor Device Simulation), vol. 33, pp. 719-726, 1990. |
| S. W. Lee, T. Y. Chan and A. T. Wu, "Circuit performance of CMOS technologies with silicon dioxide and reoxidized nitrided oxide gate dielectrics," IEEE Electron Device Lett., vol. 11, pp. 294-296, 1990. |
| A. T. Wu, T. Y. Chan, V. Murali, S. W. Lee, J. Nulman and M. Garner, "Nitridation induced donor layer in silicon and its impact on the characteristics of n- and p-channel MOSFET's," IEDM Tech. Dig., pp. 271-274, December, 1989. |
| S. W. Lee, "Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling," IEEE Trans. Computer-Aided Design, vol. CAD-8, pp. 723-729, 1989. |
| S. W. Lee, "Microscopic and macroscopic modeling of carrier mobility in MOSFETs, Device Workshop (Napa, California), April, 1989. |
| S. W. Lee, "Universal mobility characteristics of electrons in MOSFET's inversion charge layer," Intel Process Technology Conf. Tech. Dig. (Portland, Oregon), pp. 207-210, October 1988. |
| S. W. Lee and R. C. Rennick, "A compact IGFET model - ASIM," IEEE Trans. Computer-Aided Design, vol. CAD-7, pp. 952-975, 1988. |
| S. W. Lee and E. J. Prendergast, "Analytical relations for determining the base transit times and forward-biased junction capacitances of bipolar junction transistors," Solid-State Electronics, vol. 28, pp. 767-773, 1985. |
| G. M. Kull, S. W. Lee, P. Lloyd, L. W. Nagel, E. J. Prendergast and H. K. Dirks, "A unified circuit model for bipolar transistors including quasi-saturation effects," IEEE Trans. Electron Devices, vol. ED-32, pp. 1103-1113, 1985. |
| G. M. Kull, S. W. Lee, P. Lloyd, L. W. Nagel, E. J. Prendergast and H. K. Dirks, "A unified bipolar model," IEDM Tech. Dig., (Washington DC), December, 1983. |
| S. W. Lee and G. I. Haddad, "Analysis and design of CATT amplifiers," MTT, vol. 29, no. 4, 1981. |
| S. W. Lee, "Controlled avalanche transit-time triode amplifier," Thesis, University of Michigan, 1980. |
| S. W. Lee and G. I. Haddad, "Modeling of controlled avalanche transit-time triode," Electronics Lett., vol. 16, no. 6, 1980. |
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| Member of a panel at Nano Technology 2005 - "How to engage a diversified model developer community towards the same ultimate goal?" (Anaheim) - May 2005. |
| Invited speaker at Fourth Workshop on Compact Modeling, Nano Technology 2005 (Anaheim) |
| Invited speaker at 7th International Conference on Solid-State and Integrated Circuit-Technology (Beijing, People's Republic of China), October 2004 |
| Keynote speaker at Workshop on Recent Advances in Microprocessor and Communication Design Technology (IEEE Components, Packaging and Manufacturing Technology Society, Oregon Chapter), April 2004 |
| Invited speaker at the Third Workshop on Compact Modeling, Nano Technology 2003 (Boston) |
| Invited speaker and panelist at Synopsys TCAD Advisory Board Meeting (Washington DC), December 2003 |
| Invited speaker and forum panelist at the 2003 Sixth International Conference on Modeling and Simulation of Microsystems (San Francisco) |
| Plenary session speaker and forum panelist at the 2002 International Conference on Simulation of Semiconductor Processes and Devices (Kobe, Japan) |
| 1999 Design and Testing Technology Conference best paper award on "FUB SER simulation methodologies, models, and tools" (San Francisco) |
| Section chair of 1999 VLSI Technology, Systems, and Applications (Taipei, Taiwan) |
| Section chair of 1997 VLSI Technology, Systems, and Applications (Taipei, Taiwan) |
| Section chair of the 1995,7,9 VLSI Technology, Systems, and Applications (Taipei, Taiwan) |
| Invited speaker and forum panelist at the 1996 Custom Integrated Circuit Conference (Santa Clara) |
| Invited speaker at Sematech Compact Model Workshop (Austin, TX), 1995 |
| AT&T Bell Laboratories Exceptional Technical Achievement Award for developing advanced short channel MOSFET model (May, 1986) |
| AT&T Bell Laboratories Exceptional Technical Achievement Award for developing unified bipolar transistor model with quasi-saturation (December, 1984) |
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| Member of the International Advisory Committee of 2005 International Electron Device and Solid-State Circuit Conference (EDSSC'05) (Hong Kong) |
| Technical session chair at the Fourth Workshop on Compact Modeling, Nano Technology 2005 |
| Founding member of the Compact Model Council to standardize transistor models across the semiconductor industry and the official Intel representative from 1996-2001 |
| Synopsys TCAD Advisory Board since 2H'2003 |
| Member of the Advisory Board for the Electrical & Computer Engineering Department of Santa Clara University |
| Organizing committee member of the 1995,7,9 VLSI Technology, Systems, and Applications (Taipei, Taiwan) |
| Mentor for SRC research at University of Illinois, University of California at Berkeley, University of Texas (Austin), Carnegie University and University of California at Santa Cruz during 1993-1999 |
| Industry thesis advisor for University of Florida SRC Fellow during 1995-1997 |
| Regular reviewer for IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Computer-Aided Design, Solid-State Electronics and Journal of Applied Physics |
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