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Swaminathan Sivakumar
Intel Fellow, Technology and Manufacturing Group
Director, Lithography
INTEL CORPORATION
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 | 6,774,037, Method for integrating polymeric interlayer dielectric in integrated circuits, 8/10/2004 |
| 6,350,670, Method for making a semiconductor device having a carbon doped oxide insulating layer, 2/26/2002 |
| 6,365,529, Method for patterning dual damascene interconnects using a sacrificial light absorbing material, 4/2/2002 |
| 6,329,118, Method for patterning dual damascene interconnects using a sacrificial light absorbing material, 12/11/2001 |
| 6,037,255, Method for making integrated circuit having polymer interlayer dielectric, 3/14/2000 |
| 6,406,995, Pattern-sensitive deposition for damascene patterning, 6/18/2002 |
| 6,649,515, Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures, 11/18/2003 |
| 6,384,481, Single step electroplating process for interconnect via fill and metal line patterning, 5/7/2002 |
| 6,020,266, Single step electroplating process for interconnect via fill and metal line patterning, 2/1/2000 |
| 5,933,759, Method of controlling etch bias with a fixed lithography pattern for submicron critical dimension shallow trench applications, 8/3/1999 |
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