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George E. Sery
Intel Fellow, Technology and Manufacturing Group
Director, Device Technology Optimization
INTEL CORPORATION
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 | 6,624,480, Arrangements to reduce charging damage in structures of integrated circuits, 9/23/2003 |
| 6,566,716, Arrangements to reduce charging damage in structures of integrated circuits using polysilicon or metal plate(s), 5/20/2003 |
| 6,414,358, Arrangements to reduce charging damage in structures of integrated circuits, 7/2/2002 |
| 6,127,696, High voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped drain, 10/3/2000 |
| 5,668,034, Process for fabricating a high voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped drain, 9/16/1997 |
| 5,580,807, Method of fabricating a high voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped grain, 12/3/1996 |
| 5,104,819, Fabrication of interpoly dielctric for EPROM-related technologies, 4/14/1992 |
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