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Mark T. Bohr
Intel Senior Fellow, Technology and Manufacturing Group
Director, Process Architecture and Integration
INTEL CORPORATION
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 | 6762464, N-P butting connections on SOI substrates, 7/13/2004. |
| 6706584, On-die de-coupling capacitor using bumps or bars and method of making same, 3/16/2004. |
| 6703685, Super self-aligned collector device for mono and hetero bipolar junction transistors, 3/9/2004. |
| 6686247, Self-aligned contacts to gates, 2/3/2004. |
| 6671947, Method of making an interposer, 1/6/2004. |
| 6653563, Alternate bump metallurgy bars for power and ground routing, 11/25/2003. |
| 6624032, Structure and process flow for fabrication of dual gate floating body integrated MOS transistors, 9/23/2003. |
| 6617681, Interposer and method of making same, 9/9/2003. |
| 6579771, Self-aligned compact bipolar junction transistor layout, and method of making same, 6/17/2003. |
| 6566737, Passivation structure for an integrated circuit, 5/20/2003. |
| 6495897, Integrated circuit having etch-resistant layer substantially covering shallow trench regions, 12/17/2002. |
| 6392271, Structure and process flow for fabrication of dual gate floating body integrated MOS transistors, 5/21/2002. |
| 6362074, Integrated circuit processing with improved gate electrode fabrication, 3/26/2002. |
| 6337507, Salicide agglomeration fuse device with notches to enhance programmability, 1/8/2002. |
| 6143638, Passivation structure and its method of fabrication, 11/7/2000. |
| "Self-aligned contact process using low density/low-k dielectric," no. 6124191, Sep. 26, 2000. |
| 6020244, Channel dopant implantation with automatic compensation for variations in critical dimension, 2/1/2000. |
| 5976939, Low damage doping technique for self-aligned source and drain regions, 11/2/1999. |
| 5969404, Silicide agglomeration device, 10/19/1999. |
| 5911111, Polysilicon polish for patterning improvement, 6/8/1999. |
| 5734187, Memory cell design with vertically stacked crossovers, 3/31/1998. |
| 5708291, Silicide agglomeration fuse device, 1/13/1998. |
| 5536675, Isolation structure formation for semiconductor circuit fabrication," no., Jul. 16, 1996. |
| 5420051, Pre-poly emitter implant, 5/30/1995. |
| "Semiconductor field oxidation process," no. 5091332, Feb. 25, 1992. |
| 4505026, CMOS process for fabricating integrated circuits, particularly dynamic memory cells, 3/19/1985. |
| 4536947, CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors, 4/27/1985. |
| 4409259, MOS dynamic RAM cell and method of fabrication, 10/11/1983. |
| 4372034, Process for forming contact openings through oxide layers, 2/8/1983. |
| 4364075, CMOS dynamic RAM cell and method of fabrication, 12/14/1982. |
| 4282648, CMOS process, 8/11/1981. |
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| K. Zhang, et al., "A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply," International Solid State Circuits Conference, p. (2005). |
| P. Bai, et al., "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 um2 SRAM Cell," International Electron Devices Meeting, p. 657, (2004). |
| S. Thompson, et al., "A 90-nm Logic Technology Featuring Strained-Silicon," Transactions on Electron Devices, vol. 51, no. 11, p. 1790, (2004). |
| K. Mistry, et al., "Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology," Symposium on VLSI Technology, p. 50, (2004). |
| S. Thompson, et al., "A Logic Nanotechnology Featuring Strained-Silicon," Electron Device Letters, vol. 25, no. 4, p. 191, (2004). |
| K. Zhang, et al., "A SRAM Design on 65nm CMOS Technology with Integrated Leakage Reduction Schemes," Symposium on VLSI Circuits, (2004). |
| T. Ghani, et al., "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors," International Electron Devices Meeting, p. 978, (2003). |
| K. Zhang, et al., "A Fully Synchronized. Pipelined, and Re-Configurable 50Mb SRAM on 90nm CMOS Technology for Logic Applications," Symposium on VLSI Circuits, p. 253, (2003). |
| C.-H. Jan, et al., "90 nm Generation, 300mm Wafer Low k ILD/Cu Interconnect Technology," International Interconnect Technology Conference, p. 15, (2003). |
| S. Thompson, et al., "A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low-k ILD, and 1 ?m2 SRAM Cell," International Electron Devices Meeting, p. 61, (2002). |
| M. Bohr, "Nanotechnology Goals and Challenges for Electronic Applications," IEEE Transactions on Nanotechnology, vol. 1, no. 1, p. 56, (2002). |
| S. Thompson, et al., "An Enhanced 130nm Generation Logic Technology Featuring 60nm Transistors Optimized for High Performance and Low Power at 0.7-1.4 V," International Electron Devices Meeting, p. 257, (2001). |
| T. Ghani, et al., "Asymmetric Source/Drain Extension Transistor Structure for High Performance Sub-50nm Gate Length CMOS Devices," Symposium on VLSI Technology, p. 17, (2001). |
| S. Tyagi, et al., "A 130 nm Generation Logic Technology Featuring 70 nm Transistors, Dual Vt Transistors and 6 Layers of Cu Interconnects," International Electron Devices Meeting, p. 567, (2000). |
| K. Mistry, et al., "Scalability Revisited: 100 nm PD-SOI Transistors and Implications for 50 nm Devices," Symposium on VLSI Technology, p. 204, (2000). |
| M. Bohr, "Integrated Circuit Challenges, from Transistors to Packages," Solid State Devices and Materials extended abstracts, p. 14, (2000). |
| T. Ghani, et al., "Scaling Challenges and Device Design Requirements for High Performance Sub-50 nm Gate Length Planar CMOS Transistors," Symposium on VLSI Technology, p. 174, (2000). |
| T. Ghani, et al., "100 nm Gate Length High Performance / Low Power CMOS Transistor Structure," International Electron Devices Meeting, p. 415, (1999). |
| S. Yang, et al., "A High Performance 180 nm Generation Logic Technology," International Electron Devices Meeting, p. 197, (1998). |
| P. Packan, et al., "Modeling Solid Source Boron Diffusion for Advanced Transistor Applications," International Electron Devices Meeting, p. 505, (1998). |
| S. Thompson, et al., "Source/Drain Extension Scaling for 0.1um and Below Channel Length MOSFETS," Symposium on VLSI Technology, p. 132, (1998). |
| M. Bohr and Y. El-Mansy, "Technology for Advanced High-Performance Microprocessors," Transactions on Electron Devices, vol. 45, no. 3, p. 620, (1998). |
| M. Bohr, "Silicon Trends and Limits for Advanced Microprocessors," Communications of the ACM, vol. 41, no. 3, (1998). |
| M. Alavi, et al., "A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process," International Electron Devices Meeting, p. 855, (1997). |
| S. Thompson, et al., "Dual Threshold Voltages and Substrate Bias: Keys to High Performance, Low Power, 0.1um Logic Designs," Symposium on VLSI Technology, p. 69, (1997). |
| M. Bohr, et al., "A High Performance 0.25 um Logic Technology Optimized for 1.8V Operation," International Electron Devices Meeting, p. 847, (1996). |
| M. Bohr, "Scaling of High Performance Interconnects," Advanced Metallization and Interconnect Systems for ULSI Applications in 1996, Materials Research Society, p. 3, (1996). |
| S. Thompson, et al., "Linear versus Saturated Drive Current: Tradeoffs in Super Steep Retrograde Well Engineering," Symposium on VLSI Technology, p. 154, (1996). |
| G. Bai, et al., "Effectiveness and Reliability of Metal Diffusion Barriers for Copper Interconnects," Material Research Society Proceedings, vol. 403, p. 501, (1996). |
| M. Bohr, "Technology Development Strategies for the 21st Century," Applied Surface Science, vol. 100/101, p. 534, (1996). |
| M. Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI," International Electron Devices Meeting, p. 241, (1995). |
| M. Bohr, "MOS Transistors: Scaling and Performance Trends," Semiconductor International, vol. 18, no. 6, p. 75, (1995). |
| G. Raghavan, et al., "Diffusion of Copper Through Dielectric Films under Bias Temperature Stress," Thin Solid Films, vol. 262, nos. 1-2, p. 168, (1995). |
| M. Bohr, et al., "A High Performance 0.35 um Logic Technology for 3.3V and 2.5V Operation," International Electron Devices Meeting, p. 273, (1994). |
| C. Chiang, et al., "Dielectric Barrier Study for Cu Metallization," VLSI Multilayer Interconnect Conference, p. 414, (1994). |
| S. Ahmed, et al., "A Triple Diffused Approach for High Performance 0.8 um BiCMOS Technology," Solid State Technology, vol. 35, no. 10, p. 33, (1992). |
| Mohsen, et al., "The Design and Performance of CMOS 256K Bit DRAM Devices," Solid-State Circuits, vol. 19, no. 5, p. 610, (1984). |
| R. Chwang, et al., "A 70 ns High Density 64K CMOS Dynamic RAM," Solid-State Circuits, vol. 18, no. 5, p. 457, (1983). |
| K. Yu, et al., "HMOS-CMOS — A Low-Power High-Performance Technology," Solid-State Circuits, vol. 16, no. 5, p. 454, (1981). |
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| National Academy of Engineering member (2005) |
| IEEE Fellow |
| Senior sponsor for the University of Illinois campus for Intel's Academic Relations group. |
| Executive Committee for the VLSI Symposia |
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