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Intel Fellow
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Jose A. Maiz

Intel Fellow, Technology and Manufacturing Group
Director, Logic Technology
Quality and Reliability
INTEL CORPORATION
Patents
5,430,595, Electrostatic discharge protection circuit, 7/4/1995
6,596,562, Semiconductor wafer singulation method, 7/22/2003
6,787,970, Tuning of packaged film bulk acoustic resonator filters, 9/7/2004
6,794,755, Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement, 9/21/2004
Publications/Speakerships
"Semiconductor Technology Outlook and the Impact into Communications" (Invited) Jose Maiz. Presentation to the University of Navarra Telecommunication School in San Sebastian, Spain, 3 Dec, 2004
"Characterization of Multi-Bit Soft Error Events in Advanced SRAMs". Jose Maiz, Scott Hareland, Kevin Zhang and Patrick Armstrong. IEDM 2003
"Neutron Soft Error Rate Measurements in a 90-nm CMOS Process and Scaling Trends in SRAM from 0.25-mm to 90-nm Generation" P. Hazucha, T. Karnik, J. Maiz, S. Walstra, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, S. Borkar. IEDM 2003
"Correlation Between Stress Relaxation and Electromigration in Cu/ Low-K Lines" D. Gan, S. Yoon, P.Ho, J.Leu, J. Maiz, T. Scherban, Advanced Metallization Conference AMC-2003
"Nanotechnologies for Computing and Communications" (invited) Presentation to the 2002 DCIS conference. Santander, Spain
"Nanotechnologies for Computing and Communications" (invited) Presentation to the 2002 Basque Science and Technology Week. San Sebastian, Spain
"Electromigration Lifetime and Critical Void Volume" J. He, Z. Suo, T. Marieb, J. Maiz, Appl. Phys. Lett., Vol 85, No 20, 15 Nov 2004
"Silicon Scaling Trends. Test Implications and Research Opportunities" Intel Test Research mtg, Santa Clara, CA, 7 Nov 2003.
"Beyond Planar CMOS. A Reliability Perspective" (Invited) Jose Maiz. AVS Symposium, Nov 3-8, Denver CO, 2002
"From Micro to Nanotechnology. A perspective from the Semiconductor world" (Invited), Jose Maiz. Presentation to the Conference launching the CMIC institute. June 14, 2002. San Sebastian Spain
"Impact of CMOS process scaling and SOI on the soft error rates of logic processes," Scott Hareland, Jose Maiz, Mohsen Alavi, Kaizad Mistry, Steve Walstra, and Changhong Dai, Symposium on VLSI Technology, June 12-14, 2001, Kyoto, Japan
"CMOS Process Scaling Trends and their impact on soft error rates of logic processes," ,(Invited ) Scott Hareland, S. Walstra, C. Dai, K. Mistry, J. Maiz, and M. Alavi 2001 IEEE Memory Technology, Design and Testing Workshop, San Jose, CA, USA, August 6-7, 2001.
"Neutron-SER Modeling & Simulation for 0.18?m CMOS Technology," Changhong Dai, Nagib Hakim, Steve Walstra, Scott Hareland, Jose Maiz, Scott Yu, and Shiuh-Wuu Lee, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Athens, Greece, September 5-7, 2001
"Intels Risk Assessment Methodology" Jose Maiz Invited Presentation to Sandia National Lab Senior Staff. Albuquerque NM, Feb 2001
"Cross Sectional Nanoindentation: A new technique for thin film interfacial adhesion characterization" J.M Sanchez, S. El-Mansy, B. Sun, T. Scherban, N. Fang, D. Pantuso, W. Ford, M.R. Elizalde, J.M. Martinez-Esnaola, A. Martin-Meizoso, J. Gil-Sevillano , M. Fuentes, J. Maiz.. Acta Mater. Vol 47, No 17, pp 4405-4413, 1999
"Metal-ceramic thin film adhesion characterization by cross-sectional nanoindentation" M.R. Elizalde, J.M. Sanchez, S. El-Mansy, B. Sun, W. Ford, J.M. Martinez-Esnaola, A. Martin-Meizoso, T. Scherban, D. Pantuso, N. Fang, J. Gil-Sevillano, M. Fuentes and J. Maiz. Acta Mat. Sevilla, Spain 1999
"Alpha-SER Modeling & Simulation for Sub-0.25um CMOS Technology," Changhong Dai, Nagib Hakim, Scott Hareland, Jose Maiz, and Shiuh-Wuu Lee, 1999 Symposium on VLSI Circuits, Kyoto, Japan, pp. 81-82, June 17-19, 1999.
"A high performance 180 nm Generation Logic Technology" S. Yang, S. Ahmed, B. Arcot, R. Arghavani, P. Bai, S. Chambers, P. Charvat, R. Cotner, R. Gasser, T. Ghani, M. Hussein, C. Jan, C. Kardas, J. Maiz, P. McGregor, B. McIntyre, P. Nguyen, P. Packan, I. Post, S. Sivakumar, J. Steigerwald, M. Taylor, B. Tufts, S. Tyagi, M. Bohr, IEDM 1998
"Cross-Sectional Nanoindentation for thin film interfacial adhesion characterization" J.M Sanchez, S. El-Mansy, B. Sun, W. Ford, R. Elizalde, J.M. Martinez, A. Martin, C. Blanco, J. Gil, M. Fuentes, J. Maiz.
"Parametric degradation of P-Channel Transistors with scaled Gate Oxide" (Invited) S. Jacobs, P. Aminzadeh, B. Woolery, J. Maiz, SRC/Sematech Topical Research Conference in Rel. 1998
"Methods for Reducing Soft Errors in Deep Submicron Integrated Circuits," K. Zhang, S. Hareland, B. Senyk, and J. Maiz, Proceedings of the Fifth International Conference on Solid-State and Integrated-Circuit Technology (ICSICT'98), Beijing, China, pp. 516-519, Oct. 21-23, 1998.
"Predicting Soft Error Rates in Advanced Semiconductor Devices," (Invited) Scott Hareland, Jose Maiz, and Changhong Dai, SRC Topical Research Conference on Reliability, Austin, TX, October 26-28, 1998.
"Characterization of Electromigration under bi-directional (BC) and Pulsed Unidirectional (PDC) currents" Jose Maiz. 1989 IEEE Proc. Int. Reliability Physics Symp. pp 220-228, Phoenix, AZ
"Characterization of Electromigration under bi-directional (BC) and Pulsed Unidirectional (PDC) currents" Jose Maiz. Invited Presentation to the 1989 Wafer Level Reliability Workshop. Lake Tahoe, Ca
"A resistance change methodology for the study of Electromigration in Al-Si interconnects" Jose Maiz, Inigo Segura. 1988 IEEE Proc. Int. Reliability Physics Symp. pp 209-215, Monterrey, Ca,1987
"Electromigration testing of Ti/Al-Si metallization for Integrated circuits" Jose Maiz & Babak Sabi, 1987 IEEE Proc. Int. Reliability Physics Symp. pp 145
"A resistance change methodology for the study of Electromigration in Al-Si interconnects" Jose Maiz, Inigo Segura. 1988 IEEE Proc. Int. Reliability Physics Symp. pp 209-215, Monterrey, Ca
"Electromigration testing of Ti/Al-Si metallization for Integrated circuits" Jose A. Maiz & Babak Sabi. 1987 IEEE Proc. Int. Reliability Physics Symp. pp 145
Professional Affiliations
Member of the IEEE
Guest Co-Editor of the IEEE Transactions on Devices and Materials Reliability special issue on Soft Errors. Planned for Summer 2005
Member of the Advisory Board to the CEIT Research Institute
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