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Gregory F. Taylor
Intel Fellow, Technology and Manufacturing Group
Director, Mixed Signal Circuit Technology
INTEL CORPORATION
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 | 6,792,489, Multistage configuration and power setting, 9/14/2004 (with Edward P. Osburn and Ananda Sarangi) |
| 6,777,970, AC testing of leakage current in integrated circuits using RC time constant, 8/17/2004 (with Tawfik R. Arabi, Srirama Pedarla, Patrick Elwer, and Dan Murray) |
| 6,771,134, Frequency control for clock generating circuit, 8/3/2004 (with Keng L. Wong, Hong-Piao Ma, Chee How Lim, and Edward A. Burton) |
| 6,747,470, Method and apparatus for on die voltage fluctuation detection, 6/8/2004 (with Ali Muhtaroglu, Kent Callahan, and Tawfik Arabi) |
| 6,748,549, Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock, 6/8/2004 (with Chi-Yeu Chao, Chee How Lim, Keng L. Wong, and Songmin Kim) |
| 6,727,597, Integrated circuit device having C4 and wire bond connections, 4/27/2004 (with George L. Geannopoulos) |
| 6,717,455, Apparatus and Method to Use a Single Reference Component in a Master-Slave Configuration for Multiple Circuit Compensation, 4/6/2004 (with Usman A. Mughal, Razi Uddin, Chee How Lim, and Songmin Kim) |
| 6,691,241, Delay tuning to improve timing in multi-load systems, 2/10/2004 |
| 6,671,847, I/O Device Testing Method and Apparatus, 12/30/2003 (with Chi-Yeu Chao, Tawfik R. Arabi, and Thomas D. Barrett) |
| 6,628,157, Variable Delay Element for Use in Delay Tuning of Integrated Circuits, 9/30/2003 (with Ravishankar Kuppuswamy) |
| 6,584,591, Timing control for input/output testability, 6/24/2003 |
| 6,573,764, Method and apparatus for voltage-mode differential simultaneous bi-directional signaling, 6/3/2003 |
| 6,552,570, Input circuit with non-delayed time blanking, 4/22/2003 (with Chi-Yeu Chao) |
| 6,535,047, Apparatus and Method to Use a Single Reference Component in a Master-Slave Configuration for Multiple Circuit Compensation, 3/18/2003 (with Usman A. Mughal, Razi Uddin, Chee How Lim, and Songmin Kim) |
| 6,452,502, Method and apparatus for early detection of reliability degradation of electronic devices , 9/17/2002 (with Terrance J Dishongh, and David H. Pullen) |
| 6,453,421, Processor System with Power Supply Selection Mechanism, 9/17/2002 |
| 6,410,990, Integrated circuit device having C4 and wire bond connections, 6/25/2002 (with George L. Geannopoulos) |
| 6,396,309, Clocked sense amplifier flip flop with keepers to prevent floating nodes, 528/2002 (with Cangsang Zhao, and Chi-Yeu Chao) |
| 6,298,105, Method and apparatus for a low skew, low standby power clock network, 10/2/2001 (with Xia Dai, George L. Geannopuolos, John Orton and Keng Wong) |
| 6,236,695, Output buffer with timing feedback, 5/22/2001 |
| 6,208,169, Internal clock jitter detector, 3/27/2001 (with Keng L. Wong, Ravishankar Kuppuswamy, Douglas R. Parker, Hung-Piao Ma, Kent Callahan, and Xia Dai) |
| 6,157,206, On-chip termination, 12/5/2000 (with Jack A. Price, and Chee How Lim) |
| 6,124,755, Method and apparatus for biasing a charge pump, 9/26/2000 (with Douglas R. Parker) |
| 6,085,345, Timing control for input/output testability, 7/4/2000 |
| 6,075,285, Semiconductor package substrate with power die, 6/13/2000 (with George L. Geannopoulos and Larry E. Mosley) |
| 6,075,832, Method and apparatus for deskewing clock signals, 6/13/2000 (with George L. Geannopoulos, Keng L. Wong, and Xia Dai) |
| 5,801,561, Power-on initializing circuit, 9/1/1998 (with Keng L. Wong, Roshan J. Fernando, and Jeffrey E. Smith) |
| 5,748,033, Differential power bus comparator, 5/5/1998 (with Golnaz Kaveh and Jeffrey E. Smith) |
| 5,627,736, Power supply noise filter, 5/6/1997 |
| 5,539,337, Clock noise filter for integrated circuits, 7/23/1996 (with Jeffrey E. Smith) |
| 5,399,918, Large fan-in, dynamic, BiCMOS logic gate, 3/21/1995 (with Lawrence T. Clark) |
| 5,345,120, Swing limiting circuit for BiCMOS sense amplifiers, 9/6/1994 |
| 5,306,964, Reference generator circuit for BiCMOS ECL gate employing PMOS load devices, 4/26/1994 |
| 5,153,848, Floating point processor with internal free-running clock, 10/6/1992 (with Bob Elkind, Jay D. Lessert, James R. Peterson) |
| 4,982,352, Methods and apparatus for determining the absolute value of the difference between binary operands, 1/1/1991 (with James R. Peterson) |
| 4,972,362, Method and apparatus for implementing binary multiplication using Booth type multiplication, 11/20/1990 (with Bob Elkind, Jay D. Lessert, and James R. Peterson) |
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| Ali Muhtaroglu, Benoit Provost, Tawfik Rahal-Arabi, Greg Taylor, "I/O self-leakage test," ITC 04, October 2004, pp 903-906 |
| Tawfik Rahal-Arabi, Gang Ji, Matthew Ma, Ali Muhtaroglu, and Greg Taylor, "Development and Validation of an Electromagnetic Distributed Power Grid Model for High Frequency Microprocessors," VLSI 04, June 2004 |
| Ali Muhtaroglu, Greg Taylor, Tawfik Rahal-Arabi, "On-die droop detector for analog sensing of power supply noise," JSSC 04, April 2004, vol 39, issue 4, pp 651-660 |
| Gang Ji, Tawfik Arabi, Greg Taylor, "Design and Validation of a Power Supply Noise Reduction Technique," EPEP 03, October 2003 |
| Ananda Sarangi, Sean R. Babcock, Jeff R. Jones, Gregory F. Taylor, "Maintaining Microprocessor Compatibility across Process Generations," EPEP 03, October 2003 |
| Ali Muhtaroglu, Greg Taylor, Tawfik Rahal-Arabi, and Kent Callahan, "On-Die Droop Detector for Analog Sensing of Power Supply Noise," VLSI 03, June 2003 |
| Ananda Sarangi, Gregory F. Taylor, Rachael J. Parker, Edward P. Osburn, Patrick J. Ott, "Power Level Management in an IA32 Microprocessor," EPEP 02, October 2002 |
| Tawfik Rahal-Arabi, Greg Taylor, Matthew Ma, Jeff Jones and Clair Webb, "Design and Validation of the Core and IOs Decoupling of the PentiumŪ III and PentiumŪ 4 Processors," EPEP 02, October 2002 |
| Gang Ji, Tawfik Arabi, Greg Taylor, Mark Beiley, "A Design Methodology for the I/O Power Supply of Next Generation Packaging," EPEP 02, October 2002 |
| Tawfik Rahal-Arabi, Greg Taylor, Matthew Ma, and Clair Webb, "Design & Validation of the PentiumŪ III and PentiumŪ 4 Processors Power Delivery," VLSI 02, June 2002, pp 220-223 |
| Altaf Hasan, Ananda Sarangi, Christopher S Baldwin, Robert L Sankman, Gregory F Taylor, "High Performance Package Designs for a 1 GHz Microprocessor," IEEE Transactions on Advanced Packaging, November 2001, pp 470-476 |
| Greg Taylor, Craig Deutschle, Tawfik Arabi, Brian Owens, "An Approach to Measuring the Power Supply Impedance of Microprocessors," EPEP 01, October 2001, pp 211-214 |
| Ananda Sarangi, Gang Ji, Tawfik Arabi, Gregory F. Taylor, "Design and Performance Evaluation of PentiumŪ III Microprocessor Packaging," EPEP 01, October 2001, pp 291-294 |
| Ravi Kuppuswamy, Kent Callahan, Keng Wong, Dan Ratchen, Greg Taylor, "On-die Clock Jitter Detector for High Speed Microprocessors," VLSI 01, 6/14/2001, pp 187-190 |
| Tawfik Rahal-Arabi, Greg Taylor, "A JTAG Based AC Leakage Self Test," VLSI 01, 6/14/2001, pp 205-206 |
| Altaf Hasan, Ananda Sarangi, Christopher S Baldwin, Robert L Sankman, Gregory F Taylor, "High Performance Package Designs for a 1 GHz Microprocessor," ECTC 00, August 2000, pp 1178-1184 |
| Greg Taylor, Tawfik Arabi, Hans Greub, Richard Muyshondt, Alicia Manthe, and Payman Aminzadeh, "Reliability and Performance Tradeoffs in the Design of On-Chip Power Delivery and Interconnects," EPEP 99, 10/30/1999, pp 49-52 |
| Tawfik Arabi, Jeff Jones, Greg Taylor, and Dave Riendeau, "Modeling, Simulation, and Design Methodology of the Interconnect and Packaging of an Ultra-High Speed Source Synchronous Bus," EPEP 98, October 1998, pp 8-11 |
| Greg Taylor, Tawfik Arabi, Ken Hose, Jeff Jones, Songmin Kim, Ravi Kuppuswamy, Randy Mooney, Jack Price, Ananda Sarangi, "A 2MB, 3.6GB/s Back-side Bus Cache for an IA32 450 MHz Microprocessor," VLSI 98, 6/11/1998 |
| Greg Taylor, George Geannopoulos, "Microprocessor Clock Distribution," EPEP 96, 10/28/1996 |
| Greg Taylor, Keng Wong, "Power-On Contention Elimination," VLSI 96, June 1996, pp 22-23 |
| Lawrence T. Clark and Gregory F. Taylor, "High Fan-in Circuit Design," JSSC 96, January 1996, pp 91-96 |
| Lawrence T. Clark and Gregory F. Taylor, "High Fan-in Circuit Design," BCTM 94, 10/10/1994 |
| Greg Taylor, Panel: "Low Power Design," BCTM 94, 10/10/1994 |
| G. Sanguinetti, G. Taylor, and D. Clinkenbeard, "Building the world's fastest floating point processor," ASIC Technology & News, January 1991, pp 12-13 |
| G. Taylor, G. Sanguinetti, and R Lane, "An Approach to 150K Gate Low Power ECL Cell Based Integrated Circuits," ICCD 90, September 1990, pp 263-268 |
| Greg Taylor, "A 100 MHz Floating Point/Integer Processor," Hot Chips 90, Aug-90, |
| Greg Taylor, Alex Rekow, Jory Radke, Greg Thompson, "A 100 MHz Floating Point/Integer Processor," CICC 90, 5/13/1990, pp 24.5.1-4 |
| G. F. Taylor, R. H. Steinvorth, and J. F. McDonald, "An Architecture for a Video Rate Two-Dimensional Fast Fourier Transform Processor," IEEE Transactions on Computers, September 1988, Vol 37, No 9, pp 1145-1148 |
| Bob Elkind, Jay Lessert, Jim Peterson, and Greg Taylor, "A Sub 10 ns Bipolar 64 Bit Integer/Floating Point Processor Implemented on Two Circuits," BCTM 87, September 1987, pp 101-104 |
| Bob Leibowitz and Greg Taylor, "ECL gains ground in battle against CMOS, Computer Design," 4/1/1987, pp 91-95 |
| J. F. McDonald, R. H. Steinvorth, A. S. Bergendahl, G. F. Taylor, "Fabrication and Performance Considerations for Gallium Arsenide Wafer Scale Integration," ICCD 85, October 1985, pp 400-405 |
| R. H. Steinvorth, G. F. Taylor, J. F. McDonald, A. S. Bergendahl, "Wafer Scale Integration of a Video Rate Fuzzy Golay Processor," ICCD 85, October 1985, pp 672-677 |
| G. F. Taylor, Lt. B. J. Donlan, J. F. McDonald, A. S. Bergendahl, R. H. Steinvorth, "The Wafer Transmission Module - Wafer Scale Integration Packaging," CICC 85, May 1985, pp 55-58 |
| S. Bergendahl, J. F. McDonald, R. H. Steinvorth, G. F. Taylor, "Thick Film Stripline Micro Transmission Line Interconnections for Wafer Scale Integration," Electrochemical Society Spring Meeting, May 1985, pp 311-312 |
| Lt. B. J. Donlan, J. F. McDonald, G. F. Taylor, R. H. Steinvorth, A. S. Bergendahl, "Computer-Aided Design and Fabrication for Wafer Scale Integration," VLSI Design, April 1985 |
| G. F. Taylor, R. H. Steinvorth, J. F. McDonald, "An Architecture for a Wafer Scale Integration Video Rate Two Dimensional Fast Fourier Transform Processor," ICCD 84, October 1984, pp 623-628 |
| J. Donlan, G. F. Taylor, R. H. Steinvorth, A. S. Bergendahl, J. F. McDonald, "Wafer Scale Integration Using Discretionary Microtransmission Line Interconnections," Wafer Scale Integration, 1986, chapter 2.3, pp 31-45 |
| S. Bergendahl, B. J. Donlan, J. F. McDonald, R. H. Steinvorth, G. F. Taylor, "A Thick Film Lift-Off Technique for High Frequency Interconnection in Wafer Scale Integration," VLSI Multilevel Interconnect Conf, 1985 |
| R. H. Steinvorth, G. F. Taylor, J. F. McDonald, T. Hunter, "An Architecture for a Video Rate Fuzzy Golay Processor," Int Conf on Parallel Proc, 1985 |
| S. Bergendahl, J. F. McDonald, R. H. Steinvorth, G. F. Taylor, "Thick Film Stripline Micro Transmission Line Interconnections for Wafer Scale Integration," VLSI Science and Technology/1985, 1985, pp 175-184 |
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