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Clair Webb
Intel Fellow, Technology and Manufacturing Group
Director, Circuit Technology
INTEL CORPORATION
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 | 6,762,464, N-p butting connections on SOI substrates, 7/13/2004 |
| 5,430,595, Electrostatic discharge protection circuit, 7/4/1995 |
| 5,293,603, Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path, 3/8/1994 |
| 5,228,134, Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus, 7/13/1993 |
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