 |
Robert S. Chau
Intel Senior Fellow, Technology and Manufacturing Group
Director, Transistor Research and Nanotechnology
INTEL CORPORATION
|
|
|
|
|
 |
|
 |
7,005,366 Tri-gate devices and methods of fabrication |
|
6,998,686 Metal-gate electrode for CMOS transistor applications |
|
6,974,764 Method for making a semiconductor device having a metal gate electrode |
|
6,974,738 Nonplanar device with stress incorporation layer and method of fabrication |
|
6,974,733 Double-gate transistor with enhanced carrier mobility |
|
6,972,228 Method of forming an element of a microelectronic circuit |
|
6,970,373 Method and apparatus for improving stability of a 6T CMOS SRAM cell |
| 6,952,040 Transistor structure and method of fabrication |
| 6,939,815 Method for making a semiconductor device having a high-k gate dielectric |
| 6,933,589 Method of making a semiconductor transistor |
| 6,914,295 Tri-gate devices and methods of fabrication |
| 6,909,151 Nonplanar device with stress incorporation layer and method of fabrication |
| 6,900,481 Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors |
| 6,897,134 Method for making a semiconductor device having a high-k gate dielectric |
| 6,897,098 Method of fabricating an ultra-narrow channel semiconductor device |
| 6,893,927 Method for making a semiconductor device with a metal gate electrode |
| 6,890,807 Method for making a semiconductor device having a metal gate electrode |
| 6,887,800 Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction |
| 6,887,762 Method of fabricating a field effect transistor structure with abrupt source/drain junctions |
| 6,887,395 Method of forming sub-micron-size structures over a substrate |
| 6,885,084 Semiconductor transistor having a stressed channel |
| 6,869,889 Etching metal carbide films |
| 6,864,145 Method of fabricating a robust gate dielectric using a replacement gate flow |
| 6,861,318 Semiconductor transistor having a stressed channel |
| 6,858,478 Tri-gate devices and methods of fabrication |
| RE38,674 Process for forming a thin oxide layer |
| 6,825,506 Field effect transistor and method of fabrication |
| 6,812,086 Method of making a semiconductor transistor |
| 6,809,017 Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication |
| 6,797,556 MOS transistor structure and method of fabrication |
| 6,787,440 Method for making a semiconductor device having an ultra-thin high-k gate dielectric |
| 6,777,759 Device structure and method for reducing silicide encroachment |
| 6,765,273 Device structure and method for reducing silicide encroachment |
| 6,713,358 Method for making a semiconductor device having a high-k gate dielectric |
| 6,696,345 Metal-gate electrode for CMOS transistor applications |
| 6,696,327 Method for making a semiconductor device having a high-k gate dielectric |
| 6,667,251 Plasma nitridation for reduced leakage gate dielectric layers |
| 6,667,232 Thin dielectric layers and non-thermal formation thereof |
| 6,653,700 Transistor structure and method of fabrication |
| 6,645,831 Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide |
| 6,621,131 Semiconductor transistor having a stressed channel |
| 6,620,713 Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication |
| 6,617,210 Method for making a semiconductor device having a high-k gate dielectric |
| 6,617,209 Method for making a semiconductor device having a high-k gate dielectric |
| 6,610,615 Plasma nitridation for reduced leakage gate dielectric layers |
| 6,597,046 Integrated circuit with multiple gate dielectric structures |
| 6,566,727 N2O nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress |
| 6,541,343 Methods of making field effect transistor structure with partially isolated source/drain junctions |
| 6,538,278 CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
| 6,518,155 Device structure and method for reducing silicide encroachment |
| 6,514,879 Method and apparatus for dry/catalytic-wet steam oxidation of silicon |
| 6,373,112 Polysilicon-germanium MOSFET gate electrodes |
| 6,326,664 Transistor with ultra shallow tip and method of fabrication |
| 6,261,925 N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress |
| 6,221,789 Thin oxides of silicon |
| 6,214,679 Cobalt salicidation method on a silicon germanium film |
| 6,198,142 Transistor with minimal junction capacitance and method of fabrication |
| 6,191,016 Method of patterning a layer for a gate electrode of a MOS transistor |
| 6,165,826 Transistor with low resistance tip and method of fabrication in a CMOS process |
| 6,140,251 Method of processing a substrate |
| 6,124,171 Method of forming gate oxide having dual thickness by oxidation process |
| 6,121,100 Method of fabricating a MOS transistor with a raised source/drain extension |
| 6,048,769 CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
| 6,046,494 High tensile nitride layer |
| 5,908,313 Method of forming a transistor |
| 5,891,809 Manufacturable dielectric formed using multiple oxidation and anneal steps |
| 5,856,697 Integrated dual layer emitter mask and emitter trench for BiCMOS processes |
| 5,783,478 Method of fabricating a MOS transistor having a composite gate electrode |
| 5,780,346 N2O nitrided-oxide trench sidewalls and method of making isolation structure |
| 5,763,922 CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
| 5,710,450 Transistor with ultra shallow tip and method of fabrication |
| 5,633,202 High tensile nitride layer |
| 5,625,217 MOS transistor having a composite gate electrode and method of fabrication |
| 5,488,003 Method of making emitter trench BiCMOS using integrated dual layer emitter mask |
| 5,434,093 Inverted spacer transistor |
| 5,244,843 Process for forming a thin oxide layer |
|
|
|
|
|
|
|
|
S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T.J. Phillips, D. Wallis, P. Wilding and R. Chau, “85nm Gate Length Enhancement and Depletion mode InSb Quantum Well Transistors for Ultra High Speed and very Low Power Digital Logic Applications,” International Electron Devices Meeting (IEDM) Technical Digest, 2005, pp. 783-786. |
| R. Chau, S. Datta, A. Majumdar, “Opportunities and Challenges of III-V Nanoelectronics for Future High-speed, Low-power Logic Applications,” Technical Digest, IEEE Compound Semiconductor Integrated Circuit Symposium (2005 IEEE CSICS), Palm Springs, CA., Nov. 2005, pp. 17-20. |
| R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar and M. Radosavljevic, “Applications of High-K Gate Dielectrics and Metal Gate Electrodes to Enable Silicon and Non-Silicon Logic Nanotechnologies,” Microelectronic Engineering, Vol. 80, June 2005, pp. 1-6. |
| R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, “Emerging Silicon and Non-Silicon Nanoelectronic Devices: Opportunities and Challenges for Future High-Performance and Low-Power Computational Applications,” Proceedings of Technical Papers, IEEE VLSI-TSA International Symposium on VLSI Technology, Hsinchu, Taiwan, April 2005, pp. 13-16. |
| R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, "High-K/Metal-Gate Stack and Its MOSFET Characteristics," IEEE Electron Device Letters, Vol. 25, No. 6, June 2004, pp. 408-410. |
| R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, "30nm Physical Gate Length CMOS Transistors with 1.0ps n-MOS and 1.7ps p-MOS Gate Delays," International Electron Devices Meeting (IEDM) Technical Digest, 2000, pp. 45-48. |
| R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz and M. Radosavljevic, "Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications," IEEE Transactions on Nanotechnology, Vol. 4, No. 2, March 2005. |
| R. Chau, J. Kavalieros, B. Doyle, A. Murthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds and M. Doczy, "A 50nm Depleted- Substrate CMOS Transistor (DST)," IEDM Technical Digest, 2001,pp. 621-624. |
| R. Chau, M. Doczy, B. Doyle, S. Datta, G. Dewey, J. Kavalieros, B. Jin, M. Metz, A. Majumdar and M. Radosavljevic, "Advanced CMOS Transistors in the Nanotechnology Era for High-Performance, Low-Power Logic Applications," Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (ICSICT), Beijing, China, Oct. 2004, pp. 26-30. |
| R. Chau, B. Boyanov, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros and M. Metz, "Silicon Nano-transistors for Logic Applications," Physica E, Low-Dimensional Systems and Nanostructures, Vol. 19, Issues 1-2, July 2003, pp. 1-5. |
| R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani and S. Datta, "Advanced Depleted-Substrate Transistors: Single-gate, Double-Gate and Tri-gate," Extended Abstracts of the International Conference on Solid-State Devices and Materials (SSDM), Nagoya, Japan, 2002, pp. 68-69. |
| R. Chau, S. Datta, M. Doczy, J. Kavalieros and M. Metz, "Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-K," Extended Abstracts of International Workshop on Gate Insulator (IWGI), Tokyo, Japan, Nov. 2003, pp. 124-126. |
| R. Chau, R. Arghavani, M. Alavi, D. Douglas, R. Green, S. Tyagi, J. Xu, P. Packan, S. Yu, C. Liang, "Scalability of partially depleted SOI technology for sub-0.25um logic applications," IEDM Technical Digest, 1997, pp. 591-594. |
| R. Chau, "Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors," Proceedings of the American Vacuum Society 5th International Conference on Microelectronics and Interfaces (ICMI), Santa Clara, March 2004, pp. 1-3. |
| D. Barlage, J. O'Keeffe, J. Kavalieros, M. Nguyen and R. Chau, "Inversion MOS Capacitance Extraction for High-Leakage Dielectrics Using a Transmission Line Equivalent Circuit," IEEE Electron Device Letters, Vol. 21, No. 9, Sept. 2000, pp. 454-456. |
| R. Chau and J. Marcyk, "A New CMOS Transistor Architecture to Improve Drive Performance and Reduce Parasitic Leakages," Nikkei Microdevices, p.83-88, No. 200, Feb 2002 (in Japanese). |
| D. Barlage, R. Arghavani, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, A., Murthy, B. Roberds, P. Stokley and R. Chau, "High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics," IEDM Technical Digest, 2001, pp. 231-234. |
| B. Doyle, R. Arghavani, D. Barlage, S. Datta, M. Doczy, J. Kavalieros, A. Murthy and R. Chau, "Transistor Elements for 30nm Physical Gate Length and Beyond," Intel Technology Journal, Volume 6, Issue 2, May 2002. |
| R. Chau, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros and M. Metz, "Silicon Nano-Transistors and Breaking the 10nm Physical Gate Length Barrier," Conference Digest of 61st Device Research Conference, Salt Lake City, Utah, June 2003, pp. 123-126. |
| B.S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T.; Linton, A. Murthy, R. Rios, and R. Chau, "High Performance Fully-Depleted Tri-Gate CMOS Transistors," IEEE Electron Device Letters, Vol. 24, No. 4, April 2003, pp. 263-265. |
| S. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Letters, Vol. 25, No. 4 , April 2004, pp. 191 - 193. |
| B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios and R. Chau, "Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout," VLSI Technology Digest of Technical Papers, June 2003, pp. 133-134. |
| R. Chau, "Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications," Proceedings of 4th IEEE Conference on Nanotechnology (IEEE-Nano 2004), Munich, Germany, Aug. 2004. |
| T. Ashley, A. Barnes, L. Buckle, S. Datta, A. Dean, M. Emeny, M. Fearn, D. Hayes, K. Hilton, R. Jefferies, T. Martin, K. Nash, T. Philips, W. Tang, P. Wilding and R. Chau, "Novel InSb-based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications," Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology, Beijing, China, Oct. 2004, pp. 2253-2256. |
| S. Datta, J. Brask, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, M. Metz, A. Majumdar, M. Radosavljevic and R. Chau, "Advanced Si and SiGe Strained NMOS and PMOS Transistors with High-K/Metal-Gate Stack,"Proceedings Bipolar/BiCMOS Circuits and Technology Meetings (BCTM), Sept. 2004, pp. 194-197. |
| S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, N. Zelick and R. Chau, "High Mobility Si/SiGe Strained Channel MOS Transistors with HfO2/TiN Gate Stack," IEDM Technical Digest, 2003, pp. 653-656. |
| S. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr and Y. El-Mansy, "A 90nm Logic Technology Featuring Strained-Silicon," IEEE Transactions on Electron Devices, Vol. 51, No. 11, Nov. 2004, pp. 1790-1797. |
| R. Chau, "30nm and 20nm Physical Gate Length CMOS Transistors,"Extended Abstracts of Silicon Nanoelectronics Workshop, Kyoto, Japan, 2000, pp. 2-3. |
| M. Bohr, S. U. Ahmed, L. Brigham, R. Chau, R. Gasser, R. Green, W. Hargrove, E. Lee, R. Natter, S. Thompson, K. Weldon, S. Yang, "A High Performance 0.35um Logic Technology for 3.3V and 2.5V Operation," IEDM Technical Digest, 1994, pp. 273-276. |
| Y.H. Lee, L. Yau, E. Hansen, R. Chau, B. Sabi, S. Hossaini, B. Asakawa, "Hot-Carrier Degradation of Submicrometer p-MOSFET's with Thermal/LPCVD Composite Oxide," IEEE Transactions on Electron Devices, Vol. 40, No. 1, Jan 1993, pp. 163-168. |
| B. Jin, S. Datta, G. Dewey, M. Doczy, B. Doyle, K. Johnson, J. Kavalieros, M. Metz, U. Shah, N. Zelick and R. Chau, "Mobility Enhancement in Compressively Strained SiGe Surface Channel pMOS(FET) with HfO2/TiN Gate Stack," Proceedings of the ECS 2004 Joint International Meeting, SiGe: Materials Processing and Devices, Hawaii, Oct. 2004, pp. 111-122. |
| Y.H. Lee, R. Chau, L. Yau, E. Hansen, B. Sabi, S. Hui, P. Moon, G. Vandentop, "Correlation of Plasma Process Induced Charging with Fowler Nordheim Stress in P- and N-channel Transistors," IEDM Technical Digest, 1992, pp. 65-68. |
| Panelist of the 2001 VLSI Technology Symposium Rump Session on "High-K Gate Dielectrics: Is it Necessary? If So, When, What, How?" in Kyoto, Japan — June 2001. |
| Panel member of the 2001 International Electron Devices Meeting (IEDM) Panel Discussion on "The 10-nm MOSFET Barrier" in Washington, DC — Dec. 2001. |
| Panel member of the 2001 Silicon Nanoelectronics Workshop Panel Discussion on "Prospects of Novel CMOS Device Structures" in Kyoto, Japan — June 2001. |
| Speaker of the 5th Topical Research Conference on Reliability on "Advanced Depleted-Substrate Transistors" in Austin, Texas — Oct. 2002. |
| Speaker of the 4th International Symposium on Nanostructures and Mesoscopic Systems (NanoMES 2003) on "Silicon Nano-transistors for Logic Applications" in Tempe, Arizona — Feb. 2003. |
| Speaker of the 1st Korea-U.S. NanoForum on "Silicon Nano-transistors and Silicon Nanotechnology for High-Performance Logic Applications" in Seoul, Korea — Oct. 2003. |
| Speaker of the Nanotechnology Seminar at the Center for Nanotechnology at the University of Washington on "Nano-transistor Research for High-Performance, Low-Power Microprocessor Applications" — May 2003. |
| Speaker of the 32nd Annual Northern California Electronic Materials Symposium on "Silicon Nanotechnologies to Extend Moore's Law" — April 2004. |
| Panel member of the 4th IEEE Conference on Nanotechnology Panel Discussion on "Teaching Nanotechnology" in Munich, Germany — Aug. 2004. |
| Speaker of the Functional Engineered Nano Architectonics (FENA) Collaborative Workshop on "Silicon and Non-Silicon Nanotechnologies for High-Performance and Low-Power Transistor Applications" at UCLA — Dec. 2004. |
| Speaker of the 46th TMS Electronic Materials Conference on "New Metal Gate/High-K Dielectric Stacks for Continual Electrical Toxe Scaling and High-Performance CMOS Applications" in Notre Dame, Indiana — June 2004. |
| Panelist of the 2004 VLSI Technology Symposium Rump Session on "What's Beyond the Planar MOSFET?" in Honolulu, Hawaii — June 2004. |
| Panel member of the 2004 International Electron Devices Meeting (IEDM) Panel Discussion on "Nanoelectronics: Now or Never?" in San Francisco — Dec. 2004. |
| Speaker of the 2005 TechMakers Lecture Series at Purdue University on 'Si and Non-Si Nanotechnologies and their Benchmarking for High-Performance, Low-Power Logic Applications' — March 2005 |
| Speaker of the 2005 IEEE VLSI-TSA International Symposium on VLSI Technology on "Emerging Si and Non-Si Nanoelectronic Devices: Opportunities and Challenges for Future High-Performance and Low-Power Computational Applications" in Hsinchu, Taiwan — April 2005 |
| Speaker of the 2005 ECE Distinguished Seminar Series at The Ohio State University on "Advanced Si Nanotechnolgies and Emerging Non-Si Nanoelectronic Devices for High-Performance and Low-Power Logic Applications" — March 2005 |
| Speaker of the Microsystems Technology Laboratories (MTL) VLSI Seminar Series at MIT on "Device Scaling and Technology Challenge for High-Performance Sub-20nm Gate Length Transistors for the 45nm Logic Generation Node" — April 2001 |
| Speaker of the Solid State Technology and Devices Seminar at the University of California at Berkeley on "Transistor R&D for Logic Applications" — April 2002 |
| Speaker of the 14th Conference on Insulating Films on Semiconductors (INFOS 2005) on "Enabling Silicon and Non-Silicon Logic Nanotechnology using High-K Gate Dielectrics and Metal Gate Electrodes" in Leuven, Belgium — June 2005 |
|
|
|
|
|
|
|
