Historical CMOS Variation
There has been a trend in the CMOS literature in recent years to convey process variation as a new challenge associated with advanced CMOS technologies. While the continued decrease in the ratio of feature sizes to fundamental dimensions (such as atomic dimensions and light wavelengths) means that management of variation will play a significant role in future technology scaling, process variation is not new, but has been a continuing theme throughout semiconductor history.
Variation Sources in Advanced Technologies
Advanced process technologies are subject to a number of variation effects. Examples include highly random effects (random dopant fluctuation (RDF), line-edge and line-width roughness, line-edge and line-width roughness (LER) and (LWR), respectively, variations in the gate dielectric (oxide thickness variations, fixed charge, and defects and traps), patterning proximity effects (classical, and those associated with OPC), variation associated with polish (shallow trench isolation (STI), gate, and interconnect), variation associated with strain (wafer-level biaxial, high-stress capping layers, and embedded silicon-germanium (SiGe)), and variation associated with implants and anneals (tool-based, pocket implants, rapid-thermal anneal RTA and variation associated with poly grains).
A powerful tool for assessing process variation is locating ring oscillators routinely in all product designs. The detailed ring-oscillator data can be used to identify areas of concern for process teams to resolve. Systematic WIW variation data from ring oscillators on microprocessor product material shows that systematic variation has remained essentially constant across the last four generations. Random WIW variation data from ring oscillators shows a degradation in variation at the 65nm generation due to the lack of a gate oxide scale in that generation. This was recovered in the 45nm and 32nm generations by the use of high-k metal-gate.