Intel made a significant breakthrough in the 90nm process generation by introducing strained silicon on both the N and PMOS transistors. NMOS strain was introduced by adding a high-stress layer that wrapped around the transistor (a process sometimes named CESL, or contact etch-stop layer after the most common layer used for the stressor). PMOS strain was introduced by replacing the conventional source/drain region with strained SiGe (a process often called embedded-SiGe or e-SiGe). The addition of strain in both NMOS and PMOS enhanced the channel mobility, resulting in improved drive current (and improved performance) for both NMOS and PMOS.
Process Strain, Mobility Enhancement and Drive Current
Strain causes the Si atoms to stretch apart by ~1%. Strain provides mobility improvement in two ways. The first is by reducing the effective mass of the silicon. The second is by moving carriers to places with good effective mass (or reducing movement of carriers to places with bad effective mass).
The way this works for electrons is as follows. For a MOSFET built on the typical (100) surface, <110> channel orientation, the eqi-energy surfaces of the conduction band are oriented with two "out-of-plane" ellipsoids with good (low) effective mass and four "in-plane" ellipsoids with poor (high) effective mass. When the MOSFET is strained, the energy bands split, with the "out-of-plane" ellipsoids having lower energy. The electrons move from the high energy "in-plane" ellipsoids (with the poor effective mass) to the low energy "out-of-plane" ellipsoids (with the good effective mass). When the stress values get over ~2 GPa, the majority of the electrons are in the ellipsoids with the lowest effective mass. Low effective mass means better mobility and higher drive current for better performance. In addition, the splitting of the bands reduces scattering. Lower scattering means better mobility and higher drive current for better performance.
The way this works for holes is as follows. For a MOSFET built on the typical (100) surface, <110> channel orientation, the eqi-energy surfaces of the valence band form an unusually shaped surface, with four "wings" and four "feet." When the MOSFET is uniaxially strained, the shear components warp the bands to form an optimal "disk" or "hockey puck" eqi-energy surface. This "hockey-puck" shape has significantly lower effective mass in the direction of hole propagation, but higher effective mass in the other two directions (to improve the density of states, and to provide increased separation between the first and second subband for lower scattering). Lower effective mass and reduced scattering means better mobility and higher drive current for better performance.
Process Strain, Mobility Enhancement and Different Crystal Orientations
Three of the most critical questions facing advanced transistor design are 1. which orientation of substrate should we use? followed by 2. which direction should we point the channel? and including 3. which direction should we strain the device?
There are two common Si-crystal orientations under investigation. The first is the standard (100)-type orientation (with the standard <110> channel) and the second is the (110)-type orientation (generally with a <110> channel).
The reason for all the interest is that the best MOSFET performance for unstrained NMOS and PMOS are NOT on the same orientation. If we ignore strain, the best NMOS performance is on the standard (100) surface with the <110> orientation, while the best PMOS is on the (110) surface with the <110> orientation.
The fact that NMOS and PMOS transistors do not have the same optimal orientation is challenging, as it is difficult to fabricate two different orientations on one wafer.
However, things get a lot more interesting when we add strain. For example, for PMOS on a 100-surface (<110> channel) there is very little improvement in effective mass (and thus mobility) in moving from bulk silicon to the confinement of a MOSFET channel, BUT there is a LOT of improvement when the MOSFET channel is strained. In contrast, for PMOS on a 110-surface (<110> channel) we get a LOT of improvement in effective mass (and thus mobility) in moving from bulk silicon to the confinement of a MOSFET, BUT there is LIMITED improvement in straining the MOSFET.
This quandary is frequently expressed by a graph with strain on the X-axis, and mobility on the Y-axis, where the (100) direction has less mobility than the (110) direction at low stress, but the mobility improves faster with stress. The question, of course; is do they ever cross so that PMOS (100) strained is larger than PMOS (110) strained. If they do cross at a reasonable strain, then it doesn't make sense to use (110) silicon for a strained process. If they don't, then the question becomes whether the improvement in PMOS is worth the degradation in NMOS.
Process Strain, Mobility Enhancement and High-k Metal Gate
There is a elegant enhancement of strain possible with a replacement gate high-k metal-gate process. The two common methods for introducing a metal gate to the standard CMOS flow are "gate-first" or "replacement gate" processes. In the gate-first flow, the dual-metal processing is completed prior to the polysilicon gate deposition. The metal-gates are then subtractively etched along with the poly gates prior to S/D formation. In contrast, for the replacement gate flow, a standard polysilicon gate is deposited after the high-k gate dielectric deposition, which is followed by standard polysilicon processing through the salicide and the 1st ILD deposition. The wafer is then planarized and the dummy poly gate removed. The dual-metal gates are then deposited along with a low-resistance gate fill material. The excess metal is then polished off and followed by contact processing.
In the replacement gate process, removing the poly gate from the transistor after the stress-enhancement techniques are completed produces significant enhancement of stress.
Intel considers strain to be a well-established technology, where the introduction of 32nm represents the fourth generation of strain technology at Intel.
High Performance Hi-K + Metal Gate Strain Enhanced Transistors on (110) Silicon
45nm High-k + Metal Gate Strain-Enhanced Transistors