Anil AggarwalIntel Fellow, Software and Services Group
Director, Windows OS Client
Anil Aggarwal is an Intel Fellow and the director of Windows operating system client development in the Software and Services Group at Intel Corporation. He leads the team responsible for developing and optimizing Intel® architecture capabilities for Windows-based platforms targeted to the PC client, mobile client and Internet of Things market segments.
Aggarwal is an acknowledged expert in operating system power management and ISA interfaces. He initially joined Intel in 1989 to work on UNIX kernel and driver development. He subsequently spent three years at Sequent Computer Systems, then rejoined Intel in 1995. His responsibilities since that time have been twofold: optimize Windows for Intel architecture and optimize Intel architecture for Windows. Over the past two decades, Aggarwal has led this effort across a breadth of new and innovative user experiences, multiple device form factors, and the compressed timeline within which Intel has committed to deliver solutions.
Aggarwal holds a bachelor's degree in electrical and electronics engineering from the Birla Institute of Technology and Science in Pilani, India; and a master's degree in computer science from the University of Massachusetts at Amherst. He has been granted seven patents, with another six patents pending. His contributions to the development and optimization of Intel architecture and various versions of Windows throughout his career have led Intel to recognize him with four Intel Achievement Awards, earned in 1996, 2011, 2013 and 2014.
Boris A. BabayanIntel Fellow, Software and Services Group
Boris Babayan is an Intel Fellow and director of Architecture for the Software and Services Group at Intel Corporation. He leads worldwide efforts related to compiler technologies for Intel server products, technologies that enable applications to run on multiple computer architectures without recompiling, and helping to develop Intel security technologies. He will also be a key Intel representative to the leading Russia Academies and Universities, working to attract top talent to Intel sites located in Moscow, Nizhniy and Novosibirsk.
Babayan joined Intel in August of 2004. Prior to coming to Intel, he held numerous positions, including director of the Institute of Microprocessor Computer Systems for the Russian Academy of Science, chairman of Elbrus International, chief technological officer at the Moscow Center for SPARC Technologies and director of the Institute of Computer Technologies. From 1956 to 1996, Babayan worked at the Institute of Precise Mechanics and Computer Technology, eventually becoming chief of the hardware and software division. He completed his Ph.D. in 1964 and his doctorate of science in 1971. Babayan served as professor and chair of Computer Science at the Moscow Institute of Physics and Technology from 1996 to 2004.
Babayan has been a corresponding member of the Russian Academy of Science since 1984, has served as chairman of the Academic Council at the Institute of Microprocessor Computer Systems, RAS, and chairman of the dissertation council for awarding Ph.D. and Doctorate of Science Degrees, IMCS RAS. He is a member of the State Committee for State Prize Award of Russian Federation. He has served as a member of editorial boards for a number of technical journals, including deputy editor-in-chief of the Information Technologies and Computer Systems journal for the Russian Academy of Science.
Babayan's awards include the State Prize award for development and implementation of complex equipment for CAD, manufacturing and control of complex electronics in 1974; the Lenin Prize award for development and implementation of multiprocessor computer system Elbrus 2 in 1987; the Order of the Red Banner of Labor in1972; the Order of the October Revolution for design and development of Elbrus 1 computer in1982; and the Medal of Honor for design and development of Elbrus 90micro computer in 2000. He has published numerous book and papers on computer architecture. He was born December 20, 1933.
Genevieve BellVice President, Corporate Strategy Office
Genevieve Bell is an Intel Fellow and vice president of the Corporate Strategy Office at Intel Corporation. She leads a team of social scientists, interaction designers, human factors engineers and computer scientists focused on people's needs and desires to help shape new Intel products and technologies.
An accomplished anthropologist and researcher, Bell joined Intel in 1998. She has been granted a number of patents for consumer electronics innovations throughout her career, with additional patents in the user experience space pending, and is the author of numerous journal papers and articles. She was named an Intel Fellow in 2008.
In addition to her position at Intel, Bell is a highly regarded industry expert and frequent commentator on the intersection of culture and technology. She has been featured in publications such as Wired, Forbes, The Atlantic, Fast Company, the Wall Street Journal and the New York Times. She is also a sought-after public speaker and panelist at technology conferences worldwide for the insights she has gained from extensive international field work and research.
Her industry recognition includes being listed among the "100 Most Creative People in Business" by Fast Company in 2010, induction in the Women in Technology International Hall of Fame in 2012, and being honored as the 2013 Woman of Vision for Leadership by the Anita Borg Institute. Bell's book, "Divining a Digital Future: Mess and Mythology in Ubiquitous Computing," written in collaboration with Paul Dourish, was published by MIT Press in 2011.
Bell holds a combined bachelor's and master's degree in anthropology from Bryn Mawr College and a master's degree and Ph.D. in cultural anthropology from Stanford University, where she was a lecturer in the anthropology department from 1996 to 1998.
Ajay V. BhattIntel Fellow, Client Computing Group
Chief Systems Technologist, Client Research and Development
Ajay Bhatt is an Intel Fellow for the Client Computing Group and chief systems technologist in Client Research and Development at Intel Corporation. Currently, Bhatt is leading an architectural effort to transform the PC by working with key internal and external technology partners to develop future platform architectures and technologies. He also collaborates with key business and planning groups to position Intel at the forefront of future client platform innovation by setting company- and industry-wide impact strategies.
Bhatt is an industry-recognized technical expert in the area of Platform Architecture and I/O technologies. Bhatt joined Intel in 1990. At Intel, he has been the chief architect and co-inventor of broadly adopted technologies such as USB, Accelerated Graphics Port, PCI Express, platform power management architecture and various personal computer enhancements. The technologies he has helped developed have had profound impact on the computer industry. Bhatt currently holds 32 patents in the area of Platform architecture and I/O technologies several in various stages of filing.
Bhatt earned his master's degree from The City University of New York and currently holds 32 patents with several in various stages of filing. Bhatt, who is based in Hillsboro, Ore., is invited worldwide to give technical talks at leading universities and industry groups. His recognitions include being named one of "The Most Influential Global Indians", The Light of India Award 2012, for his contributions in advancement of science and technology, The Asian Award 2013 for outstanding achievement in Science and technology and EU Inventor award 2013 for his contributions to the development of USB.
David R. BlytheIntel Fellow, Platform Engineering Group
Chief Graphics Software Architect, Visual and Parallel Computing Group
David Blythe is an Intel Fellow for the Platform Engineering Group and chief graphics software architect for the Visual and Parallel Computing Group at Intel Corporation. He leads the development of advanced features and application programming interfaces (APIs) for Intel's processor graphics products, as well as the software architecture for Intel's processor graphics and Xeon Phi architectures.
Before joining Intel in 2010, Blythe spent 7 years at Microsoft Corporation, most recently as a partner software architect with responsibility for the architecture of Windows graphics APIs and component implementations. Earlier in his career, he was a senior system architect and co-founder of BroadOn Communications Corp. and a chief engineer at Silicon Graphics Inc.
A member of the Institute of Electrical and Electronics Engineers (IEEE) and the Association for Computing Machinery (ACM), Blythe has authored or co-authored more than 15 technical papers published in industry journals. He has been granted 15 patents, with another five patents pending, in the field of computer graphics.
Blythe holds a bachelor's and a master's degree in computer science, both from the University of Toronto.
Zdravko BoosIntel Fellow, Platform Engineering Group
Radio Smartphone System Engineering
Zdravko Boos is an Intel Fellow and an expert in Radio Smartphone System Engineering for the Platform Engineering Group at Intel Corporation. He is responsible for the development of advanced digital cellular transceiver concepts suitable for System-on-Chip (SoC) integration.
Previously with Siemens Semiconductors in 1998 and later in 1999 with spin-off semiconductor operations at Infineon, Boos worked on RF CMOS IP development, where he developed solutions for the world's first 3G CMOS transceiver used widely in mobile phones. With increased demand for highly integrated multimode, multiband mobile phones, he led successful pre-development of a single chain transmitter which enabled reduction of power amplifiers from 4:1, at the same time providing unique advantages in power consumption, chip area, shrink ability and BOM.
Prior to Siemens, Boos was with Philips Consumer Electronics Eindhoven, where he developed DAB front-ends for reference DAB452 and DAB752 receivers. Before Philips he was with Radio Industry Zagreb, developing frequency synthesizers and UHF transmitters.
Boos holds 15 US patents, he has managed the European Information Societies Technology Program, "Design Methodology and Implementation of a 3rd Generation W-CDMA Transceiver using Deep Submicron CMOS Technologies," and he has organized and managed technical co-operations with a number of universities: University of Aachen, University of California, Berkeley, University of Chalmers, ETH Zuerich, University of Erlangen, JKU Linz, TU Munich, University of Stuttgart, University of Tampere, and University of Udine where more than 20 Ph.D students earned their promotions.
Boos received his bachelor's degree in electrical engineering from University of Zagreb in 1982. He also earned his master's degree from the Eindhoven International University in 1991.
Shekhar Y. BorkarIntel Fellow, Data Center Group
Director, Extreme-scale Technologies
Shekhar Y. Borkar is an Intel Fellow and director of Extreme-scale Technologies for the Data Center Group at Intel Corporation. Borkar is responsible for directing extreme-scale research in technologies for Intel's future microprocessors.
Borkar joined Intel in 1981. He worked on the design of the 8051 family of microcontrollers, iWarp multicomputer and high-speed signaling technology for Intel supercomputers. Borkar is an adjunct member of the faculty of the Oregon Graduate Institute. He has published over 100 articles and holds 50 patents.
Borkar was born in Mumbai, India. He received a master's degree in Electrical Engineering from the University of Notre Dame in 1981, and a master and bachelor degrees in Physics from the University of Bombay in 1979.
Nigel CookIntel Fellow, Data Center Group
Chief Cloud Architect, Cloud Platforms Group
Nigel Cook is an Intel Fellow and Chief Cloud Architect for the Cloud Platforms Group at Intel Corporation. In his role, Cook will define the next generation of cloud orchestration software and help drive the cloud vision across Intel and the industry.
Prior to joining Intel in 2014, Cook spent 13 years with Hewlett Packard as Fellow and Chief Technologist, creating product concepts and architectures for cloud computing. At HP, he most recently led the re-invention of cloud infrastructure software. His efforts led to the development and rapid adoption of the HP CloudSystem Matrix product line, HP's premier private and hybrid cloud solution.
Prior to HP, Cook worked for a number of engineering companies and universities in Australia, Switzerland and the United States, in roles spanning software development, software architecture, business development, solution delivery and lab management.
Cook received a Bachelor of Engineering degree in electrical and computer engineering, and studied a Master of Engineering degree in technology management from the University of Queensland, and is currently pursuing a Master of Science degree on the intersection of cloud computing and metagenomics. In which he had published, and developed an open source project, n3phele, experimenting with cloud-based workbenches.
Cook holds several technology patents in the areas of data center resource management and storage virtualization.
Vivek K. DeIntel Fellow, Intel Labs
Director, Circuit Technology Research
Vivek K. De is an Intel Fellow and director of Circuit Technology Research in Intel Labs.
De joined Intel in 1996 as a staff engineer in Intel's Circuits Research Lab (CRL). Since that time he has led research teams in CRL focused on developing advanced circuits and design techniques for low-power and high-performance processors. In his current role as director of CRL in the Circuits and Systems Research group of Intel Labs, De provides strategic direction for future circuit technologies and is responsible for aligning Intel's circuit research with technology scaling challenges.
De has published more than 200 technical papers and holds 185 patents with 28 more patents filed (pending). He received an Intel Achievement Award for his contributions to a novel integrated voltage regulator technology. He is a Fellow of the IEEE.
Prior to joining Intel, De was engaged in semiconductor devices and circuits research at Rensselaer Polytechnic Institute and Georgia Institute of Technology, and was a visiting researcher at Texas Instruments.
De received his bachelor's degree in electrical engineering from the Indian Institute of Technology in Madras, India in 1985 and his master's degree in electrical engineering from Duke University in 1986. He received a Ph.D. in electrical engineering from Rensselaer Polytechnic Institute in 1992.
Eric DishmanIntel Fellow, Data Center Group
General Manager, Health and Life Sciences
Eric Dishman is an Intel Fellow and general manager of the Health and Life Sciences for the Data Center Group at Intel Corporation. He is responsible for driving Intel's cross-business strategy, R&D, product, and policy initiatives for health and life science solutions. His organization focuses on growth opportunities for Intel in health IT, genomics and personalized medicine, consumer wellness, and care coordination technologies in more than a dozen countries.
Dishman is widely recognized as a global leader in healthcare innovation with specific expertise in home and community-based technologies and services for chronic disease management and independent living. He is also known for pioneering innovation techniques that incorporate anthropology, ethnography, and other social science methods into the design and development of new technologies. He and his team's work have been featured in publications including the New York Times, Washington Post, Business Week, and USA Today. The Wall Street Journal named him one of "12 People Who Are Changing Your Retirement."
An internationally renowned speaker, Dishman has delivered hundreds of prominent keynotes on healthcare reform and innovation around the globe, from the Consumer Electronics Show to TED to the White House Conference on Aging to the World Health Organization. He has published dozens of articles on personal health technologies and co-authored many government reports on health information technologies and reform.
Dishman co-founded some of the world's largest research and policy organizations devoted to advancing the cause of independent living, including the Technology Research for Independent Living (TRIL) Centre, the Center for Aging Services Technologies (CAST), the Everyday Technologies for Alzheimer's Care (ETAC) program, and the Oregon Center for Aging & Technology (ORCATECH). Dishman has received numerous awards for his work in helping to shape the future of health care.
Social Networks: Dishman writes about his vision, experiences, and concerns on healthcare IT and policy issues, especially around the growth of personal health technologies for the home at:
Mark S. DoranIntel Fellow, Software and Services Group
Chief Platform Software Architect, System Software Division
Mark Doran is an Intel Fellow and the chief platform software architect within the System Software Division for the Software and Services Group at Intel Corporation. As lead architect for the Unified Extensible Firmware Interface (UEFI) program and the company's implementation of UEFI, codenamed "Tiano," he develops industry standards-based firmware for Intel architecture systems. Doran also serves as president of the UEFI Forum, a non-profit trade organization that develops the primary de jure industry standards for platform firmware.
Before assuming his current position at Intel, Doran was the program manager for the Intel boot initiative. That initiative, which involved defining a boot solution for Intel Itanium processor-based platforms, led to the Extensible Firmware Interface (EFI). Earlier in his Intel career, Doran served as manager of the Applications Solution Center, and as the developer and author of the Multiprocessor Specification (MPS), the first recipe for commodity multi-CPU, PC-compatible computers and operating systems. He joined Intel in 1994 as a software engineer for UNIX operating system development. Before coming to Intel, he was with UNIX International and served as a consultant in open systems development for The Instruction Set Ltd. in London.
Doran is the author of two books and numerous articles published in technical journals. He holds 19 patents in the field of platform firmware and system boot architecture, with another four patents pending, and he is a four-time winner of the Intel Achievement Award for technological innovation and his contributions to firmware engineering.
Doran earned a bachelor's degree in computer science with electronic engineering from University College, London University, in the United Kingdom.
Pradeep K. DubeyIntel Fellow, Intel Labs
Director, Parallel Computing Lab
Pradeep Dubey is an Intel Fellow and director of the Parallel Computing Lab, a part of the Intel Labs organization at Intel Corporation. Since 2003, he has led a team of top researchers focused on state-of-the-art research in highly parallel computing. Dubey and his team are charged with defining computer architectures that can efficiently handle new compute-intensive and data-intensive application paradigms for future computing environments, and deriving product differentiation opportunities for Intel multi-core and many-core platforms.
Dubey previously worked at Intel from 1984 to 1991. Before rejoining the company in 2003, he had served as a research staff member at IBM's T.J. Watson Research Center from 1991 to 2001. While there, he was one of the principal architects of the AltiVec multimedia extension to the Power PC architecture.
Throughout his career, Dubey has made significant contributions to the design, architecture and application performance of various microprocessors, including the IBM Power PC, the Intel386™, Intel486™, Intel® Pentium® and Intel Xeon® processors, and Intel's new Many Integrated Core (MIC) line of processors.
He holds more than 30 patents and has published more than 50 peer-reviewed technical papers. In 2012, Dubey was honored with an Intel Achievement Award for breakthroughs in parallel computing research.
Dubey earned a bachelor's degree in electronics and communication engineering from Birla Institute of Technology, India; a master's degree in electrical engineering from the University of Massachusetts at Amherst; and a Ph.D. in electrical engineering from Purdue University. He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2001 for his contributions to computer architecture supporting multimedia processing.
Wajdi K. FeghaliIntel Fellow, Data Center Group
Director, Security and Algorithms, Center of Innovation
Wajdi K. Feghali is an Intel Fellow and the director of the Security and Algorithms Center of Innovation in the Data Center Group at Intel Corporation. He leads the development of cryptography, compression, data integrity and data de-duplication hardware and software solutions with a focus on efficient performance across Intel products.
Based in Boston, Feghali joined Intel in 2000 to work on hardware cryptographic accelerators for the Intel IXP2850 network processor. Since then, he has worked on hardware acceleration technology, Intel architecture instruction set extensions and software optimizations. Feghali has directed the development of the instructions to accelerate secure hash algorithms (SHA Extensions), the Advanced Encryption Standard New Instructions (AES-NI) and public key algorithms. His contributions to the architecture and implementation of AES-NI earned him an Intel Achievement Award.
Feghali's work as an instruction set architect has led to the development of new instructions and microarchitecture enhancements for Intel® Core™, Intel® Xeon® and Intel® Atom™ processors. His work as a software and solutions architect has led to optimized software solutions for storage, networking, cloud and data center applications.
Before joining Intel, Feghali was a hardware accelerator development manager and software designer with TimeStep Corporation and Newbridge Networks Corporation.
Feghali has been granted more than 50 U.S. patents, with numerous other patents pending, and is the author of several published technical papers. He has a bachelor's degree in mathematics with a minor in computer science from the University of Ottawa in Canada.
Tryggve FossumIntel Fellow, Data Center Group
Director, Scalable Computer Architecture
Tryggve Fossum is an Intel Fellow and director of Scalable Computer Architecture for the Data Center Group at Intel Corporation. He leads a research group of engineers looking for how to best scale chip designs to support many cores on die, and to scale systems to thousands of nodes in the network. The group works with product development teams to address challenges with memory bandwidth, cache coherence, on-die interconnect, network interface, router architecture and network topology in distributed memory systems. All of this while dealing with error rates and power constraints. In recent years, Tryggve was the lead architect for an innovative Itanium server chip, and a pioneering Xeon server chip. He received an Intel Achievement award for his work on the ring interconnect for multi core architectures.
Fossum joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel.
Prior to joining Intel, Fossum held a variety of positions during 28 years of combined service to Compaq and Digital Equipment Corporation. Since 1998, he served as a Compaq Fellow and was lead architect for future versions of the Alpha microprocessor. From 1991 to 1998, Fossum led a team conducting processor and compiler technology research. Prior to this, he was a consulting engineer and helped design several VAX processors for Digital.
Fossum received a Cand Mag degree in Science from the University of Oslo in 1968.He earned his doctorate and master's degree in mathematics from the University of Illinois in 1972 and 1970, respectively. Fossum completed a post-doctorate program at the University of Illinois in 1973.
Fossum holds 37 patents on various aspects of computer design, including floating point, error handling, vector processing, multithreading and cache organization technologies.
Alan GaraIntel Fellow, Data Center Group
Chief Architect, Exascale Systems
Alan Gara is an Intel Fellow and chief architect for Exascale Systems for the Data Center Group at Intel Corporation.
Prior to joining Intel in 2011, Dr. Gara was in IBM Watson research, where he was chief architect for three generations of Blue Gene machines. The first generation Blue Gene/L machine was number one on the Top500 list from November 2004 to November 2007. Dr. Gara received a second Gordon Bell award for QCD calculations done on the Blue Gene machine in 2006. Innovations in the Blue Gene architecture have resulted in his more than 70 patents. Dr. Gara was promoted to IBM fellow in 2007. President Obama awarded IBM with the National Medal of Technology and Innovation for Blue Gene in 2009.
Gara previously joined Columbia University in 1992, where he became a member of the E690 experimental group at Fermilab. This was followed by work at the Large Hadron Collider at CERN. In parallel with this experimental physics work, he collaborated with the Columbia University theory group lead by Professor Norman Christ. This group designed and built the QCDSP supercomputer, optimized for Quantum Chromodynamics (QCD) calculations. Dr. Gara was awarded his first Gordon Bell award for this work in 1998.
Gara received his PhD in physics from the University of Wisconsin, Madison in 1987 for his work calculating the meson mass spectra utilizing a relativistic Bethe-Salpeter approach.
Martin D. GilesIntel Fellow, Technology and Manufacturing Group
Director, Transistor Technology Variation
Martin D. Giles is an Intel Fellow and the director of transistor technology variation in the Technology and Manufacturing Group at Intel Corporation. He is responsible for all aspects of understanding and mitigating transistor variation, from materials and device-level analysis to electrical characterization and circuit methodologies.
Giles joined Intel in 1994, working initially in the Technology CAD department to develop and apply advanced process models to Intel logic technologies from 0.18-micron (0.18mm) onward. In 1998, he became principal engineer and manager of the Process and Device Modeling Group. In that role, he led his team to tackle challenges such as understanding and engineering transistor stress for improved transistor performance on 90-nanometer (90nm) process technology, and moving from 2-D planar modeling to 3-D process and device models that enabled early analysis of the tri-gate transistor architecture. Starting in 2008, as a member of Intel's Process Technology Modeling organization, Giles focused on transistor variation and led teams in research, pathfinding and development to measure, model and reduce transistor variation for 14nm and subsequent generations of process technology.
Before joining Intel, Giles spent four years as an assistant professor in the electrical engineering and computer science department at the University of Michigan. Earlier in his career, he was a member of technical staff at AT&T Bell Laboratories.
Giles holds a bachelor's degree in natural sciences (physics) from the University of Cambridge, as well as a master's degree and a Ph.D., both in electrical engineering from Stanford University. He has been granted 18 U.S. patents in the field of semiconductor devices and technology, with another four patents pending. He has also authored or co-authored more than 80 technical articles, conference presentations and published book chapters. He serves on the executive committee of the International Electron Devices Meeting and is a Fellow of the Institute of Electrical and Electronics Engineers.
Knut S. GrimsrudIntel Fellow, Technology and Manufacturing Group
Director, Storage Architecture
Knut S. Grimsrud leads a research and development group responsible for mainstream and consumer storage interface definition and enabling. He is also responsible for developing new mainstream storage innovations for Intel platforms. Grimsrud and his team currently manage definition and ongoing evolution of the Serial ATA interface as well as the definition and industry enabling for the CE-ATA interface. He is also researching new applications of Flash in Intel platforms.
Grimsrud joined Intel in 1993 as a hardware engineer in the Intel Architecture Labs where his primary focus was on improving the storage performance of Intel's entry into the standard high-volume server segment. His focus transitioned to mainstream storage optimization techniques in the Platform Architecture Labs where his contributions included disk reorganization techniques for improved application launch performance. Grimsrud then drove definition of the Serial ATA disk drive interface standard and its subsequent evolutions and enhancements, which continues today under his group in the Storage Technologies Group.
Grimsrud received his bachelor's degree in electrical engineering in 1988, his master's degree in electrical and computer engineering in 1989 and his Ph.D in 1993, all from Brigham Young University. Grimsrud holds 23 U.S. patents and has received three Intel Achievement Awards and a Lifetime Achievement Award from Intel IDF. He serves as chairman of the board of directors for the Serial ATA International Organization and chairman of the steering committee of the CE-ATA Working Group.
Steven L. GrobmanIntel Fellow, Intel Security Group
Chief Technology Officer
Steve Grobman is an Intel Fellow and the Chief Technology Officer with the Intel Security Group at Intel Corporation. In this role, Grobman sets the technical strategy and direction for the company's security business across hardware and software platforms, including McAfee and Intel's other security assets.
Grobman joined Intel in 1994 as an architect in IT and has served in a variety of senior technical leadership positions during his Intel career. Before assuming his current role in late 2014, he spent a year as chief technology officer for the Intel Security Platform division and prior to that spent 2 years as CTO for Intel technologies at Intel's McAfee subsidiary to integrate security technology from the two companies.
In prior roles, Grobman served as chief security technologist for the Intel® Atom™ processor system-on-chip design group and spent 7 years as chief architect for Intel® vPro™ technology platforms. In the latter position, he led work on the solutions architecture that resulted in a business platform with unique hardware-based management and security capabilities.
Before joining Intel, Grobman spent 4 years at IBM as a solutions programmer and developer.
Grobman has published a number of technical papers and books and holds 20 U.S. and international patents in the fields of security, software and computer architecture, with another approximately 20 patents pending. He is also the recipient of two Intel Achievement Awards, the first earned in 2005 for the invention, initial architecture and strategy of the first PC embedded appliance; and the second in 2007 for the success of the Intel vPro technology platform.
Grobman earned his bachelor's degree in computer science from North Carolina State University.
Frank T. HadyIntel Fellow, Technology and Manufacturing Group
Director, Non-Volatile Memory Platform Architecture
Frank T. Hady is an Intel Fellow and director of non-volatile memory platform architecture in Intel Corporation's Technology and Manufacturing Group. He leads research and design of platform innovations for non-volatile memory as the architect of high-performance Intel solid-state drives and as manager of the research team identifying and prototyping platform-level innovations to determine the best uses for these devices.
Hady joined Intel in 1995 as a hardware engineer in the Platform Architecture Labs and has focused on platform I/O innovation throughout his Intel career. He served as Intel's chief I/O architect and has been a leader of cross-company research into shared storage architectures. Hady's research into tightly coupled heterogeneous processors led to the product line formerly codenamed "Tolapai" and Intel QuickAssist technology. Methodologies, tools and standards invented by Hady and his team have improved the way Intel and the industry measure performance, resulting in significant chipset, network processor, I/O device and network storage enhancements.
Before joining Intel, Hady was a research scientist at the Supercomputing Research Center, where he built parallel computers and researched network improvements.
Hady has authored or co-authored more than 30 published papers on topics related to networking, storage and I/O innovation. He holds 22 U.S. patents, with more patents pending, spanning heterogeneous multi-processor architecture, performance measurement techniques, networking and storage and platform I/O architectures.
A senior member of the Institute of Electrical and Electronics Engineers (IEEE), Hady received his bachelor's and master's degrees in electrical engineering from the University of Virginia, and his Ph.D. in electrical engineering from the University of Maryland.
James P. HeldIntel Fellow, Intel Labs
Director, Microprocessor and Programming Research
As director of Microprocessor and Programming Research, Jim Held leads a team conducting research in microarchitecture, parallel computing and programming systems to develop key technologies for future microprocessors and platforms.
Since joining Intel in 1990, Held has served in a variety of positions working on computer supported collaboration technology and Intel Native Signal Processing (NSP) infrastructure. He served as staff principal architect in the Media and Interconnect Technology Lab in IAL and as the Lab Director in CTG, managing the Volume Platforms Lab. As a Senior Principal Engineer in the Microprocessor Technology Lab, he conducted research on extensible processor architecture, multi-core processor architecture and helped develop Intel's virtualization technology strategy. From 2005-2011 he led a virtual team of senior architects conducting Intel Lab's Tera-Scale Computing Research.
Before coming to Intel, Held worked in research and teaching capacities in the Medical School and Department of Computer Science at the University of Minnesota. He is a Member of the IEEE Computer Society and the Association for Computer Machinery (ACM).
Held earned a B.S. in Chemical Engineering in 1972 and an M.S. (1984) and Ph.D. (1988) in Computer and Information Science, all from the University of Minnesota.
Jeffrey M. HicksIntel Fellow, Technology and Manufacturing Group
Director, Technology Reliability Pathfinding
Jeffrey M. Hicks is an Intel Fellow in the Technology and Manufacturing Group and the director of Technology Reliability Pathfinding at Intel Corporation. He manages reliability for new logic technologies and oversees reliability work that occurs during the research, definition and initial formal technology development stages. He leads a team of development engineers at the Portland Technology Development organization in Oregon.
Hicks joined Intel in 1980 as a reliability engineer working on bipolar and non-volatile memory technologies. In the three decades since, he has served in a range of quality and reliability (Q&R) functions in the United States and Europe, spanning technology development, manufacturing, product quality and customer Q&R. Before assuming his current role, he was Q&R manager for the California Technology and Manufacturing organization. Earlier in his Intel career, he managed Intel's European Quality Support Centre in Swindon, England, and served as Q&R manager for Intel's Fab 10 fabrication facility in Leixlip, Ireland.
A highly regarded semiconductor device physicist, Hicks has authored or co-authored more than 20 refereed papers for publication and has been granted four patents in semiconductor engineering disciplines. He has earned four Intel Achievement Awards: for Q&R support that led to business growth for a European customer; for developing Intel's first embedded (poly) fuse; for transistor reliability on High-k Metal Gate technology; and for contributing to improved performance and reliability on Intel's 22-nanometer (22nm) process technology.
Hicks holds a bachelor's degree in applied physics from the California Institute of Technology.
Bruce HornIntel Fellow, New Devices Group
Chief Scientist, Smart Device Innovation
Bruce Horn is an Intel Fellow and Chief Scientist for Smart Device Innovation in the New Devices Group (NDG) at Intel Corporation. He is responsible for the vision and architecture of intelligent personal devices and systems within NDG.
Previous to joining Intel, Dr. Horn was Principal Research Software Development Engineer at Microsoft Corp. where he worked on the creation and deployment of Natural Language systems for Bing, Microsoft's search engine. Before joining Microsoft, he was at Powerset Inc. where he was responsible for the computational infrastructure of the Powerset Natural Language Search System.
Horn is most widely known for his work at Apple, where he created and developed the Macintosh Finder - the first widely-used desktop graphical user interface. He began his career as a member of the Learning Research Group at the Xerox Palo Alto Research Center, where he contributed to several implementations of the Smalltalk virtual machine.
Horn earned a B.S. In Mathematical Sciences from Stanford University in 1981, and an M.S. And Ph.D. In Computer Science from Carnegie-Mellon University in 1994.
Chia-Hong JanIntel Fellow, Technology and Manufacturing Group
Director, System-on-Chip (SoC) Technology Integration
Chia-Hong Jan is an Intel Fellow and director of system-on-chip (SoC) technology integration for the Technology and Manufacturing Group. In this role, Jan manages 32nm and 22nm process technologies for all of Intel Corporation's SoC products, including ultra low power mobile Internet devices, netbook processors, consumer electronics products, embedded products, wireless communication applications and chipset/graphic processors.
Since joining Intel in 1991, Jan has held a number of technical and management positions in Portland Technology Development for 0.8um, 0.55µm, 0.35µm, 0.25µm, 0.18µm, 0.13µm, 90nm, 65nm, 45nm, 32nm and now 22nm advanced CMOS technology development. He was the rapid thermal processing (RTP) and advanced silicon deposition (ASD) group leader, working on the development of novel salicide technology, advanced gate oxide processes, source/drain junction engineering and epi SiGe technology for strained silicon. He led the team that spearheaded the integration of new salicide materials, including titanium (0.55µm), cobalt (0.18µm) and nickel into the basic logic CMOS process. He was the 90nm interconnect integration manager, and his team was the first in the industry to successfully integrate low-k ILD materials for high performance microprocessors. He was also the program manager for the 65nm low-power chipset process technology and 45nm SoC process technology for Intel® Atom™ processor –based low-power products, which were the first in industry to deploy the innovative high-k/metal gate technology on SoC.
Jan holds 37 U.S. patents in the fields of semiconductor manufacturing process and integration. He has published more than 40 technical papers related to CMOS processing technology. Jan has received three Intel Achievement Awards and is the recipient of the 2008 Distinguished Achievement Award of the College of Engineering at the University of Wisconsin-Madison.
Jan received his bachelor's degree in chemical engineering from National Taiwan University in 1982. He also earned his MBA from National Taiwan University in 1986. He then earned his master's degree and Ph.D. in materials science from the University of Wisconsin-Madison in 1988 and 1991, respectively.
Hong JiangIntel Fellow, Platform Engineering Group
Chief Media Architect and Director, Visual and Parallel Computing Group Media Architecture Team
Hong Jiang is an Intel Fellow and the chief media architect for the Platform Engineering Group and director of the Visual and Parallel Computing Group's Media Architecture Team at Intel Corporation. He leads the media architecture of processor graphics and its derivatives, including the definition of media hardware and software assets and the group's technology roadmap. As chief media architect - a position he has held since 2002 - Jiang earned recognition for co-inventing the programmable Intel graphics architecture that has powered all Intel client PCs since 2006.
In a previous role as a platform architect at Intel, Jiang contributed to and co-edited key interconnect and video-coding standards. Earlier, as a video architect, he led video decoder and video capture hardware and software definition and implementation for chipset graphics products. Jiang joined Intel in 1996 in the then-newly formed graphics operation in Intel's PCI Component Division.
Jiang has more than 20 journal and conference publications to his name, and he holds 38 issued patents and 44 pending patents in the fields of imaging and visual computing, graphics and media architecture, video compression, video processing, inter-chip communication, computer system architecture and processor architecture. He was honored with an Intel Achievement Award in 2011 for outstanding innovation in delivering an industry-leading media architecture.
Jiang received his bachelor's degree in electrical engineering from the University of Science and Technology of China. He holds a master's degree in electrical engineering from Academia Sinica, Institute of Electronics, Beijing; and a second master's degree in engineering science from Dartmouth College. He earned his Ph.D. in electrical engineering from the University of Illinois at Urbana-Champaign.
Stephan J. JourdanIntel Fellow, Platform Engineering Group
Director, System-on-Chip Architecture
Stephan J. Jourdan is an Intel Fellow in the Platform Engineering Group and serves as the director of system-on-chip (SoC) architecture at Intel Corporation. He is responsible for the definition and architectural development of Intel's SoC microprocessors for tablets and phones.
Jourdan joined Intel in 1997 to work on the microarchitecture of the Intel® Pentium® 4 processor. Before assuming his current position, he served as chief architect and led a team of colleagues in the definition of low-power versions of the fourth-generation Intel® Core™ processor family formerly code-named "Haswell." Earlier in his Intel career, he was lead architect for the client products based on the Intel processor family formerly code-named "Nehalem." In 2008, Jourdan was honored with an Intel Achievement Award for his contributions to architectural and circuit innovations on Nehalem.
Jourdan holds more than 50 patents, with additional patents pending, in the area of high-performance and power-efficient computing. He earned his master's degree and Ph.D. in computer sciences from the University of Toulouse in France and his MBA degree from the University of Oregon.
Shivnandan D. Kaushik (Shiv)Intel Fellow, Software and Services Group
General Manager, Windows OS Division
Shivnandan (Shiv) Kaushik is an Intel Fellow in the Software and Services Group and general manager of the Windows OS Division at Intel Corporation. Kaushik directs work on the definition of IA ingredient, platform and firmware interfaces and optimizations for Microsoft operating systems.
Kaushik joined Intel in 1995 as a senior software engineer and has served in a number of software engineering and management roles. He is an expert in the design of IA platform hardware and firmware interfaces. In this role, he has made optimizations for features introduced on Intel processors and platforms since the Pentium® Pro and contributions to industry standard firmware specifications.
Kaushik has over 50 patents granted or pending in the areas of system software and platform architecture. He has received four Intel Achievement Awards and led his organization to win the Intel Quality Award in 2015.
Kaushik received a bachelor's degree in computer science and engineering from the Indian Institute of Technology, Bombay in 1990. He earned his master's degree and doctorate in computer and information science from The Ohio State University in 1991 and 1995, respectively.
Sailesh KottapalliIntel Fellow, Platform Engineering Group
Director, Data Center Processor Architecture
Sailesh Kottapalli is an Intel Fellow and the director of data center processor architecture in the Platform Engineering Group at Intel Corporation. He leads a team of architects responsible for developing the architecture of Intel® Xeon®, Intel® Xeon Phi™ and Intel® Atom™ server processors. He is also the chief architect for processor system agent architecture, system-on-chip (SoC) architecture standards and architecture convergence across the various product lines.
Kottapalli joined Intel in 1996 as a design engineer working on the first Intel® Itanium® processor, then code-named "Merced." Subsequently, he served as lead engineer for several Intel Itanium and Intel Xeon processor evaluations, and more recently, as lead architect for a series of Intel Xeon server processors. His work in this area earned Kottapalli an Intel Achievement Award for delivering record generational performance improvements in a high-end server product.
An active participant in industry and internal conferences, Kottapalli has authored or co-authored several published technical papers, delivered talks and taken part in roundtables and panel discussions. He has also been granted approximately three dozen patents in processor architecture, with additional patents pending.
Kottapalli holds a bachelor's degree in computer science from Andhra University in India and a master's degree in computer engineering from Virginia Tech.
Lakshman KrishnamurthyIntel Fellow, New Devices Group
Director, Applied Innovation Engineering
Lakshman Krishnamurthy is an Intel Fellow in the New Devices Group and the director of applied innovation engineering at Intel Corporation. He is responsible for research and engineering efforts to create wearable devices and apply new technologies to these devices. He leads a multi-disciplinary team that integrates user experience, new technologies, materials, industrial design and software to enable rapid concept creation and applications. His efforts led to the first set of wearables marking Intel's foray into this space, including a heart rate-sensing ear bud, an audio platform that redefines the personal digital assistant experience, and a smart wireless charging bowl.
Krishnamurthy joined Intel in 1997 as a software engineer in the Intel Architecture Labs, now called Intel Labs. His research has contributed to many Intel product areas, including Internet media streaming protocols, digital television and integration of wireless radio technologies in Intel PC platforms. He also pioneered concepts in the Internet of Things arena by leading the deployment of sensing networks in an Intel factory and on an oil tanker in the North Sea.
Before moving to the New Devices Group, Krishnamurthy proposed a vision of small wearables enabling human beings to live productive, happy and healthy lives. He pursued that vision with a string of projects that produced features such as wireless display capabilities for Intel's integrated sensor hub.
Krishnamurthy has authored or co-authored more than 20 publications in refereed conferences and journals, and his many inventions throughout his career have resulted in more than 30 granted and pending patents.
Krishnamurthy received a bachelor's degree in instrumentation technology from Sri Jayachamarajendra College of Engineering in Mysore, India, and earned his Ph.D. in computer science from the University of Kentucky.
David J. KuckIntel Fellow, Software and Services Group
Director, Hardware and Software Codesign Tools
David J. Kuck is an Intel Fellow in the Software and Solutions Group (SSG) and director of Hardware and Software Codesign Tools for Intel Corporation. He is currently working on the HW/SW codesign of architectures and applications based on performance, energy and cost. Under Kuck's leadership, SSG produced industry leading parallel tools including ThreadChecker, ThreadProfiler, and OpenMP.
Kuck founded KAI in 1979, which produced the KAP vectorization and parallelization tools. KAI was acquired by Intel in 2000. He is an emeritus faculty member of the Computer Science and Electrical and Computer Engineering departments of the University of Illinois at Urbana-Champaign, and was director of the Center for Supercomputing Research and Development.
Kuck holds a bachelor's degree in electrical engineering from the University of Michigan, and Ph.D. from Northwestern University. He is a fellow of the AAAS, ACM, and IEEE, and member of the NAE. He has won a number of awards, most recently the 2010 ACM-IEEE Kennedy Award, and the IEEE Computer Society's 2011 Computer Pioneer Award.
Belliappa (Belli) KuttannaIntel Fellow, New Technology Group
Director, Platform Architecture
Belliappa (Belli) Kuttanna is an Intel Fellow and platform architect in the New Technology Group at Intel Corporation. He is responsible for leading the definition of next-generation compute platforms and systems.
Kuttanna was the chief architect of the Intel® Atom processor family for the Platform Engineering Group. In that role he was responsible for leading the architectural definition of Intel® Atom processors. Kuttanna also lead the development of Intel® Quark CPU architecture. He was the lead architect for the system-on-chip (SoC) in Medfield, the first x86-based phone platform. He was additionally responsible for performance analysis of some Intel® Atom processor-based phone and tablet SoCs.
Since the start of his career in 1989, Kuttanna also held positions in the areas of ASIC and processor design and architecture at Texas Instruments Inc., Motorola Inc., Sun Microsystems Inc. and Qualcomm Inc.
Kuttanna holds 28 issued patents and was the recipient of an Intel Achievement Award in 2008.
Kuttanna earned his bachelor's degree in electronics and communication engineering from Karnataka Regional Engineering College in India and a master's degree in electrical engineering from Texas A&M University.
William R. MagroIntel Fellow, Software and Services Group
Chief Technologist, Technical Computing Software
William Magro is an Intel Fellow in the Software and Services Group and the chief technologist for technical computing software at Intel Corporation. He serves as the technical lead and strategist for Intel's high-performance computing (HPC) and workstation software and provides technical computing software requirements for Intel product roadmaps.
Magro joined Intel in 2000 with the acquisition of Kuck & Associates Inc. (KAI). He began his Intel career as director of the Parallel Applications Center, where he was responsible for enabling parallel applications to use Intel's emerging multi-core technology. From 2006 to 2010, he served as director of high-performance computing software solutions and led Intel's efforts in HPC software products. Magro's work in HPC and parallel computing has earned him two Intel Achievement Awards.
Before joining KAI in 1997, Magro spent 3 years as a post-doctoral fellow and staff member at the Cornell Theory Center at Cornell University, where he performed research in quantum physics and evaluated future supercomputing systems.
A recognized expert in HPC, Magro has authored numerous articles published in technical and academic journals and holds four patents, with another seven patents pending. He is a member of the Association for Computing Machinery and the co-chair of the InfiniBand Trade Association Technical Working Group.
Magro holds a bachelor's degree in applied and engineering physics from Cornell University and a master's degree and Ph.D. in physics from the University of Illinois at Urbana-Champaign.
Asit K. MallickIntel Fellow, Software and Services Group
Chief Architect, Open Source Technology Center
Asit K. Mallick is an Intel Fellow and chief architect in the Open Source Technology Center at Intel Corporation. He is responsible for Intel's engagement with open source-based operating systems and virtualization software. Mallick oversees the platform feature definitions, optimizations and system software architecture for operating systems such as Linux, Android and Chrome OS; and for virtual machine monitors (VMMs) such as the Xen hypervisor and the KVM virtualization infrastructure.
An expert in platform architecture and software interfaces, Mallick joined Intel in 1992 as a senior software engineer responsible for enabling processor and platform features in operating systems such as OS/2. In the past 20-plus years of his Intel career, Mallick has worked with the Linux operating system. He leads Intel's enabling efforts for Linux on Intel architecture processor-based platforms. Mallick's prior roles at Intel include leading the architecture definition and enabling of Xen with Intel® Virtualization Technology, and leading the enabling of 64-bit Linux for Intel® 64 architecture. Earlier in his Intel career, he was one of the lead architects in the development of 64-bit Linux for the Intel® Itanium® processor. He has received two Intel Achievement Awards.
Mallick earned a bachelor's degree in electronics and electrical engineering from the Indian Institute of Technology, Kharagpur and a master's degree in electrical communication engineering from the Indian Institute of Science, Bangalore. He holds seven patents in the area of platform architecture and system software, with an additional patent pending. He has also authored specifications for OS and VMM developers.
Alberto J. MartínezIntel Fellow, Platform Engineering Group
Chief Architect, Embedded Subsystems and IP Group
Alberto J. Martínez is an Intel Fellow and the chief architect of the Embedded Subsystems and IP Group (EIG) in the Platform Engineering Group at Intel Corporation. He is also the lead architect for Intel's Audio, Voice and Speech Center of Excellence. Martínez oversees the architecture and definition of integrated compute subsystems such as signal, acoustic and security processors; and I/O interfaces such as USB, storage, PCI and many others shared among multiple system-on-chip (SoC), silicon and software products.
Martínez joined Intel in 1994 to work on the definition and development of verification procedures for OEM platforms based on Intel® architecture processors. In 1998, he was named lead software architect for chipset architecture and spent the next 12 years focused on defining software and firmware architecture for I/O subsystems and embedded computing subsystems. His responsibilities in that role included the enabling and deployment of the Windows, OSx, Android and Chrome operating systems. His accomplishments at Intel include the architecture and design of integrated audio with the AC'97 audio codec, which brought low-cost music playback to the PC industry. Martínez also contributed to the architecture and design of Intel® High Definition Audio, Intel® Smart Sound Technology and the I/O power architecture for 5th generation Intel® Core™ processors. He earned an Intel Achievement Award for his architectural work on the USB 3.0 host controller for 3rd generation Intel Core chipsets.
Before joining Intel, Martínez was a staff engineer at Epson America Corporation. Earlier in his career, he managed the Research and Development Printer Division at Epson Venezuela S.A. and served as an engineering consultant at ECOSEN C.A., also in Venezuela.
Martínez holds a bachelor's degree in electronics engineering from Simón Bolívar University in Sartenejas, Venezuela; and a master's degree in electrical engineering from California State University, Sacramento. He has been granted nine patents, with another patent pending, in a range of computing and system architecture topics, including power management, security, signal processing and operating system services. He has also authored or co-authored 10 technical publications on similar topics.
Wesley D. McCulloughIntel Fellow, Platform Engineering Group
Director, Ingredient Productization and Customer Enabling, Microprocessor Development Group
Wesley D. McCullough is an Intel Fellow for the Platform Engineering Group and director of Ingredient Productization and Customer Enabling for the Microprocessor Development Group at Intel Corporation.
In this role, McCullough oversees the development and productization of Intel® Architecture Core products (mobile, desktop, workstation and server computing segments) from the time they first see silicon through product release qualification and high-volume manufacturing. He leads Intel Corporation's post-silicon teams in identifying and solving product issues, optimizing products, enabling and supporting high-volume manufacturing, and providing expert customer enabling support.
Since joining the company in 1989, McCullough has held technical and leadership positions in microprocessor development including key roles in the Intel® 486 DX2 processor, the Intel® Pentium® Pro processor, and the Intel® Pentium 4 processor family of processors. Most recently, McCullough was a key technologist in the development of Intel's latest "Nehalem" generation of microprocessors, the Intel® Core™ i7, Intel® Core™ i5, and Intel® Xeon® processor 5500 series. For Westmere (the 2-core client version of the Nehalem family), McCullough was the chief technologist responsible for product definition as well as overseeing verification, testing and customer support issues. He holds three patents and has written or contributed to 10 papers or publications.
McCullough received his bachelor's degree in electrical engineering from Brigham Young University, Utah, in 1990.
Anand S. MurthyIntel Fellow, Technology and Manufacturing Group
Director, Strained Silicon Process Technology
Anand Murthy is an Intel Fellow and director of Strained Silicon Process Technology at Intel's Portland Technology Development Group in Oregon. He is responsible for leading the pathfinding process development team for advanced strained transistors based on novel epitaxial deposition for 14nm CMOS logic technology node.
Murthy joined Intel in 1995 and was responsible for developing embedded SiGe epitaxial deposition process for industry-leading first-ever strained PMOS transistors at the 90nm technology node. Murthy subsequently led the pathfinding process development for strain enhancement in subsequent technology nodes. He also led the process development and implementation of a novel raised S/D EPI film for NMOS transistors at 32nm node, a first at Intel and in the industry.
Murthy is the recipient of four Intel Achievement Awards and the 2008 SEMI North American Award for "Process Integration of Strain-enhanced Mobility Techniques for CMOS Transistors." He has co-authored papers in more than 40 technical publications and holds 58 patents, the majority of them granted for his work in epitaxial deposition to enable strained transistors.
Murthy earned a bachelor's degree from the Indian Institute of Technology, Banaras Hindu University, in 1987. He earned a master's degree from The Ohio State University in 1988, and a Ph.D. in materials science and engineering from University of Southern California in 1993.
David J. O'BrienIntel Fellow, Platform Engineering Group
Chief Technologist, Manufacturing Development Organization
David J. O'Brien is an Intel Fellow in the Platform Engineering Group and the chief technologist for the Manufacturing Development Organization at Intel Corporation. He is responsible for silicon manufacturing development and system usage optimizations, and for fostering new business opportunities for Intel through product manufacturing systems and product definition.
Since joining Intel in 1989, O'Brien has been a product development engineer dedicated to silicon manufacturing development that melds architecture, design, validation and reliability. His Intel career began with the 80960 family of microcontrollers, followed by multiprocessor system cache memory and the Intel® Pentium® Pro processor. He later turned his attention to the first and subsequent generations of the Pentium 4 family of processors. Most recently, O'Brien has focused his technical capabilities on the first and fourth generations of Intel® Core™ processors. A principal engineer since 2000, he has accrued extensive expertise in product bin splits, platform implications and product testing in high-volume manufacturing.
O'Brien holds six patents in the field of semiconductor testing and is frequently invited to speak at industry events on the topic of semiconductor manufacturing and testing. At Intel, his contributions have been honored three times — in 2003, 2004 and 2014 — with Intel Achievement Awards, the company's highest technical award.
O'Brien holds a bachelor's degree in electrical engineering from Arizona State University and is a member of the Institute of Electrical and Electronics Engineers.
Paul A. PackanIntel Fellow, Technology and Manufacturing Group
Director, Transistor Technology Development
Paul Packan is an Intel Fellow, Technology and Manufacturing Group, and director of Transistor Technology Development. In this role, he currently leads Intel Corporation's 15nm device technology group. Among his recent successes is delivering Intel's 32nm device technology to production including Intel's second-generation high-k and fourth-generation strained silicon technologies.
Packan joined Intel in 1992, leading the process and device simulation group in applying TCAD simulations to develop and optimize Intel's 0.35µm, 0.25µm and 0.18µm process technologies focusing on device and process architecture. In 1998, he began leading the process and device modeling group, developing advanced models for ion implantation, dopant diffusion, carrier transport, carrier mobility and quantum effects to enable exploration of novel process and device technologies. In 2001, he assumed ownership of the compact device modeling group, delivering the industry's first surface potential-based compact device model for circuit level simulation to enable accurate digital, analog, RF and noise modeling.
He has been issued more than 10 patents in the area of transistor architecture and has authored or co-authored more than 30 papers.
Packan received his bachelor's degree in electrical engineering from the University of Washington in 1984, and his master's and doctorate in electrical engineering from Stanford University in 1985 and 1991, respectively.
David B. PapworthIntel Fellow, Law and Policy Group
Director, Microprocessor Product Development
David B. Papworth is an Intel Fellow, Law and Policy Group and the director of Microprocessor Product Development for Intel Corporation. Papworth designs next-generation microprocessor architectures, including concept development, performance analysis, resolution of detailed design and compatibility issues, and interaction with software developers. He also provides technical direction and expertise in moving new designs and proliferations from silicon to production and launch.
Papworth joined Intel in 1990 as a staff VLSI architect. He was one of the lead architects of the Pentium® Pro microprocessor. In 1994, he became principal processor architect, responsible for the system debugging of the Pentium Pro processor. His team received an Intel Achievement Award and an Intel Quality Award in 1996 for the Pentium Pro microarchitecture. He also receive an Intel Achievement Award in 1997, for the design and use of the P6 Microcode Update facility. Papworth is named as inventor or co-inventor on 56 patents for microprocessors, computers, and computer systems.
Papworth was born in Hancock, Mich., in 1956. He received his bachelor's degree in Electrical Engineering from the University of Michigan, Ann Arbor, in 1979. Prior to Intel, Papworth worked at Multiflow Computer as director of hardware engineering, and at Prime Computer as a principal engineer designing digital logic for super-minicomputers.
Krishna ParatIntel Fellow, Technology and Manufacturing Group
Director, NAND Cell Research and Development
Krishna Parat is an Intel Fellow and the director of NAND cell research and development in the Intel Non-Volatile Memory Solutions Group. He oversees the NAND Flash Device Group and is currently responsible for developing Intel's NAND Flash scaling roadmap beyond the 20-nanometer (20nm) node.
Parat has played a key role in developing Intel's Flash memory technologies. He co-led the team responsible for the research and development of Intel's industry-leading 20nm NAND Flash technology. From 2006 to 2008 he co-led the cell development for Intel's 50nm and 34nm NAND Flash technology. From 1996 to 2005, he co-led the development of several generations of Intel's NOR Flash technology, beginning with 0.25 micron through 90nm. Parat joined Intel in 1991 as a device engineer working on 0.60micron NOR Flash technology.
A recognized expert in non-volatile memory technology, Parat is frequently invited to speak and present papers at industry-sponsored workshops and symposiums. He has written or co-authored more than 30 presentations and papers since 1987. Parat has also been honored with three Intel Achievement Awards - two for his work on NOR Flash and one for establishing Intel's NAND cell scaling leadership with 34nm technology.
Parat holds 16 U.S. patents and has filed more than a dozen additional patent applications that are currently pending. An active member of the Institute of Electrical and Electronics Engineers (IEEE), Parat in 1985 earned his B. Tech. degree in electrical engineering from the Indian Institute of Technology in Chennai, India. He also holds a master's degree in electrical engineering and a Ph.D. in electrical engineering, both from Rensselaer Polytechnic Institute.
Devadas D. PillaiIntel Fellow, Technology and Manufacturing Group
Director, Operational Decision Support Technology
Intel Fellow Devadas (Dev) Pillai is the Director of Operational Decision Support Technology in the Logic Technology Development group, based in Chandler, Arizona. He is currently responsible for development and proliferation of manufacturing simulation technology and mathematical modeling & optimization capabilities across Intel's wafer fabrication, sort, assembly and test factories worldwide.
Pillai is Intel's first fellow whose technical expertise spans production simulation, robotics and factory automation. He has been honored many times by his industry peers as one of the most influential engineers who drove the vision and industry direction for large scale factory automation in semiconductor manufacturing.
Pillai introduced the use of computer simulation technology for Intel's factory operational designs beginning in 1986. From 1989 to 1994, he was the Design Engineering Manager of the Automated Material Handling Systems Group and led the company's successful 150mm and 200mm robotic transport systems development. From 1994 to 2000, he was Factory Integration Manager who coordinated Intel's highly successful 300mm production equipment, facilities and automation interface standardization and interoperability development with the worldwide consortia. Prior to his current position, he managed Intel's Enabling Technologies and Solutions group that was responsible for yield, fault isolation and failure analysis tools, process and production control systems, knowledge management capabilities and machine learning programs. Prior to Intel, Pillai was a development engineer at Ford Trucks.
Pillai is the recipient of two Intel Achievement Awards. In 2000, he was recognized by the National Academy of Engineering at the Frontiers of Engineering conference. He has written more than 90 peer-reviewed technical papers and presentations in IEEE, ISSM, SME, JES, IIE and SEMI publication in the fields of factory automation, 300mm factory design, and simulation modeling. He has also written a section on automation in the McGraw Hill Encyclopedia of Science and Technology and has co-authored a chapter in the Handbook of Semiconductor Manufacturing Technology, published by Marcel Dekker.
Pillai received his master's degree in Industrial Engineering specializing in computer-aided processes, from Arizona State University in December 1983 and his bachelor's degree in Mechanical Engineering from the National Institute of Technology, Calicut, India, in 1980.
Valluri RaoIntel Fellow, Technology and Manufacturing Group
Director, Analytical and Microsystems Technologies
Dr. Valluri Rao is an Intel Fellow and director of Analytical and Microsystems Technology in Intel's Technology and Manufacturing Group. He is responsible for research into heterogeneous integration of different technologies for Intel's CMOS Silicon and SOC platforms. Rao is also an IEEE Fellow.
Rao joined Intel in 1983 and pioneered numerous silicon characterization techniques for microprocessor performance, debug and yield enhancement. Some of these techniques included electron beam based and Ultra-fast optical measurement from microprocessors and silicon micromachining methods for on chip reconfiguring and repairing of circuits for product validation. Rao, who was named an Intel Fellow in 2000, worked on Intel microprocessors starting from the 80386 to the first generation of Itanium processors. Beginning in 2001, Rao initiated Intel's MEMS work by establishing a research and development team to develop reconfigurable RF front end systems for multi radio coexistence. To enable this, advanced RF MEMS switches and novel silicon integration schemes were developed.
He also initiated Intel's early work on optical interconnects and led Intel's first Opto-Electronics research committee for overseeing university-based optical research.
Rao holds more than 80 issued patents. He has earned three Intel Achievement Awards for his work on microprocessor characterization and has published more than 20 external and 10 internal papers.
Rao graduated in 1975 with a first class honors in the Electrical Sciences Tripos from Jesus College, Cambridge University, from where he also received master's (1978) and Ph.D. (1979) degrees in electrical engineering. He was a post-doctoral research fellow at the Cambridge University Engineering Department from 1979 to 1983.
Robert L. SankmanIntel Fellow, Technology and Manufacturing Group
Director, Package Pathfinding, Assembly Test Technology Development
Bob Sankman is an Intel Fellow and director of package pathfinding in the Assembly Test Technology Development group at Intel Corporation. He is responsible for directing the definition of packaging and assembly activities for Intel's advanced logic products.
Before assuming his current role, Sankman served as the pathfinding and planning manager for the Assembly Test Technology Development group, where he was responsible for defining packaging technology to support all Intel logic processes. Earlier in his Intel career, Sankman was the group's design and core competency manager, a position in which he designed product packages and provided modeling support for assembly technology development. Sankman joined Intel in 1980 as a process engineer during the startup of Intel's Fab 6 facility in Chandler, Ariz.
Sankman holds 29 patents in the field of electronic packaging and has been honored with three Intel Achievement Awards - two in the area of semiconductor fabrication and one in semiconductor packaging. He has also contributed his expertise to numerous papers.
Sankman earned his bachelor's degree in chemical engineering from the University of Illinois in 1980.
Richard SchenkerIntel Fellow, Technology and Manufacturing Group
Director, Novel Patterning
Richard Schenker is an Intel Fellow and the director of novel patterning in the Technology and Manufacturing Group at Intel Corporation. He works within the group's Components Research organization and leads a team developing novel patterning methods to enable continued scaling of Moore's Law. Schenker specializes in developing patterning-enhancement techniques for future lithography generations and design technology co-optimization. He is also a member Intel's design rule definition team.
Schenker joined Intel in 1997 as part of the advanced lithography group within the Components Research organization. Over the course of his Intel career, his contributions in this area have earned him three Intel Achievement Awards. Schenker pioneered the use of alternating phase-shift masks for gate patterning at Intel. He has also worked on several resolution-enhancement methods and novel patterning techniques implemented by Intel for density scaling.
Schenker holds a bachelor's degree in electrical engineering from the University of Wisconsin-Madison; and a master's degree and Ph.D. in electrical engineering, both from the University of California, Berkeley. In the course of earning his doctorate, he was part of the UC Berkeley team that won the 1997 Technical Excellence Award from the Semiconductor Research Corporation.
He has been granted 13 patents in lithography and patterning, and has co-authored more than 20 publications in the field of lithography, patterning and design technology co-optimization.
Mark K. SeagerIntel Fellow, Data Center Group
Chief Technology Officer, Technical Computing Group
Mark K. Seager is an Intel Fellow in the Data Center Group and the chief technology officer for the Technical Computing Group at Intel Corporation. His work focuses on the development, deployment and use of exascale high-performance computing (HPC) systems with technology based on broadly available HPC systems. Considered the next leap forward in supercomputing, exascale systems will be capable of performing a billion billion calculations per second.
Seager joined Intel in 2011 from Lawrence Livermore National Laboratory (LLNL), bringing the company 28 years of experience in parallel processing. Most recently at the research facility, he led advanced technology at the Livermore Computer Center and established his reputation as a leading mind in petascale computing system design, procurement and integration. Seager's accomplishments during his LLNL tenure include being influential in the development of the U.S. Department of Energy Accelerated Strategic Computing Initiative's computing and problem-solving environment strategies, including shaping the initiative's platform strategy. He was also a founding member of OpenSFS, a consortium to provide support for Lustre on Linux for the HPC community, and served as LLNL's representative to the OpenSFS board.
A recognized expert in the supercomputing industry, Seager has earned numerous awards for his technical contributions in the field, including the 2004 Edward Teller Fellowship Award.
Seager earned his bachelor's degree in mathematics and astrophysics from the University of New Mexico at Albuquerque and his Ph.D. in numerical analysis from the University of Texas at Austin. He was named an Intel Fellow in 2015 and represents Intel on the OpenSFS board of directors. Seager has authored or co-authored nearly 40 publications and has made presentations at more than 50 U.S. and international conferences in the HPC arena. He is a member of the Institute of Electrical and Electronics Engineers, the Association for Computing Machinery, and the Society of Industrial and Applied Mathematics.
Vivek K. SinghIntel Fellow, Technology and Manufacturing Group
Director, Computational Lithography
Vivek Singh is an Intel Fellow and director of computational lithography in Intel's Technology and Manufacturing Group.
He is responsible for all of Intel's CAD and modeling tool development in full chip OPC, lithography verification, rigorous lithography modeling, next-generation lithography selection, inverse lithography technologies and double patterning. He also represents Intel on several external Design for Manufacturability (DFM) forums, and is currently chairman of the SPIE DFM Conference.
Singh joined Intel in 1993 as a modeling applications engineer, was appointed team leader for the Resist and Applications Group in 1996, and was appointed overall leader of the Lithography Modeling Group in 2000.
He holds 13 patents, has published 38 technical papers and won the Intel Achievement Award in 2007.
Singh graduated from the Indian Institute of Technology in Delhi with a bachelor's degree in chemical engineering in 1989. He earned a master's degree in chemical engineering in 1990, a Ph.D. minor in electrical engineering in 1993, and a Ph.D. in chemical engineering in 1993, all from Stanford University.
Ronak SinghalIntel Fellow, Platform Engineering Group
Director, CPU Computing Architecture
Ronak Singhal is an Intel Fellow and the director of CPU computing architecture in the Platform Engineering Group at Intel Corporation. He has overall responsibility for the architecture development of the CPU core intellectual property (IP) present in Intel's product families, such as products based on the Intel® Xeon®, Intel® Core™, Intel® Atom™ and Intel® Quark™ processors.
Singhal joined Intel in Oregon in 1997, spending his first year in the company's Rotation Engineers Program. He has since been a member of the CPU architecture team. He dedicated the early years of his Intel career to performance analysis and validation for the Intel® Pentium® 4 processor-based family of products. Subsequently, he led the overall performance efforts on the CPU architectures formerly code-named "Nehalem" and "Westmere," and led the core development effort for the CPU architecture formerly code-named "Haswell." He also led the server architecture development for Haswell and for the first 14-nanometer (14nm) server architecture.
He won Intel Achievement Awards in 2008 and 2014, the first for architecture and circuit innovations in the development of Nehalem.
Singhal holds bachelor's and master's degrees in electrical and computer engineering, both from Carnegie Mellon University. He has been granted 11 patents in the area of CPU architecture, with additional patents pending. He has also co-authored approximately 10 technical articles published in industry journals and speaks frequently on the topic of CPU architecture at industry forums.
Joseph M. SteigerwaldIntel Fellow, Technology and Manufacturing Group
Director, Chemical Mechanical Polish Technology
Joe Steigerwald is an Intel Fellow and director of Chemical Mechanical Polish Technology, Intel Technology and Manufacturing Group. He is responsible for pathfinding, development, and transfer to high volume manufacturing of advanced chemical metal polish (CMP) and metals deposition modules for Intel's 32nm, 22nm, and 16nm logic and advanced memory technologies.
Steigerwald originally joined Intel in 1988 as a fab etch engineer. He left for a brief time to pursue advanced electrical engineering degrees and has been with the company continuously since 1995. He has held a number of leadership roles in the company's Portland Technology Development organization, primarily in the CMP area. His work in CMP has lead to major advancements in this critical technology, enabling key elements of Intel's silicon process architecture.
Steigerwald has written one book and one book chapter and hold three patents for advances in his CMP area of expertise. His work has appeared in more than a dozen journal publications and he has made numerous technical conference and workshop presentations.
Originally from Upstate New York, Steigerwald received his bachelor's degree in electrical engineering from Clarkson University in 1988. He received his masters and doctorate degrees in electrical engineering from Rensselaer Polytechnic Institute in 1993 and 1995, respectively.
Michael J. StetterIntel Fellow, Platform Engineering Group
Chief Platform Technology Officer
Michael Stetter is an Intel Fellow and chief platform technology officer for the Platform Engineering Group at Intel Corporation. Stetter develops products and solutions for mobile communications, including smartphones, tablets and entry-level mobile phones. Stetter is responsible for external silicon foundry technology strategy and technology platform target-setting, as well as for leading a strategic initiative to enable product cost leadership for entry/value smartphone and next-generation LTE slim modem products on in-house technologies.
Stetter joined Intel in 2011 when the company completed its acquisition of Infineon Technologies' wireless solutions business. Earlier in his career, he spent 13 years at Siemens HL/Infineon in various technology research and development positions. During his tenure there, he proposed and implemented the multi-sourcing strategy that enabled simultaneous sourcing from Charted and Taiwan Semiconductor Manufacturing Company for 65-nanometer technology generations. Later, United Microelectronics Corp. was added as well.
From 1998 to 2001, Stetter was part of a manufacturing development alliance between IBM, Infineon and Samsung in East Fishkill, N.Y., where his responsibilities included leading the back-end and front-end multinational integration teams. While Stetter was in that role, the management team representing the three alliance partners recognized him as "Inventor of the Year." Other positions in his career included leading a research team at GSI Darmstadt (Gesellschaft für Schwerionenforschung) and a 3-year, internationally funded research project at CERN (the European Organization for Nuclear Research).
Stetter holds 11 patents in the field of plasma physics and CMOS process integration, and has authored roughly 18 papers and publications on the same topic. He received his master's degree in physics from the University of Erlangen in Nürnberg, Germany, and his Ph.D. in physics from Friedrich-Alexander University Erlangen, also in Nürnberg.
Kenneth StewartIntel Fellow, Platform Engineering Group
Chief Wireless Technologist
Dr. Kenneth (Ken) Stewart is an Intel Fellow and chief wireless technologist for the Platform Engineering Group at Intel Corporation. Over the past 25 years in the industry, Stewart has contributed strongly to fundamental research in mobile wireless technologies including GSM, CDMA, WCDMA and LTE, and to the development of the associated 3GPP international wireless standards, particularly HSPA, LTE and LTE-Advanced. He has engineered and reduced to practice base station and mobile solutions based on the same technologies.
Most recently, Stewart was CTO for TE Connectivity's wireless division, where he drove innovation and product development for advanced small cell and distributed antenna systems, wavelength division multiplexed fiber distributed radio access networks, coordinated multipoint transmission systems and solutions for broadband wireless access infrastructure.
Previously, Stewart was vice president of Standards and Research at Motorola Mobile Devices, where he was responsible for international standards and research work in areas ranging from radio access networks, through multimedia systems to mobile applications and services. He served as advisor to Motorola Mobile Devices senior leadership on fundamental technical and strategic issues regarding the performance and evolution of radio access networks and multimedia technology.
Stewart has held the position of Motorola Dan Noble Fellow and served on Motorola's Science Advisory Board. He holds more than 35 issued patents, with multiple patents pending. He is a graduate of the Institute for Communications and Signal Processing at the University of Strathclyde, where he is also Visiting Professor.
Gregory F. TaylorIntel Fellow, Platform Engineering Group
Chief Architect, Mixed Signal IP Solutions Group
Greg Taylor is an Intel Fellow and Chief Architect in IPG's Mixed Signal IP Solutions Group. His interests include Systems on a Chip, Analog/Mixed Signal circuits, and Wireless.
Taylor joined Intel in 1991 and has held several senior design engineering positions working on 10 generations of microprocessors including members of Intel's Pentium®, Pentium® II, Pentium® III, and Intel NetBurst® microarchitecture families. Prior to joining Intel, he worked as a principal engineer at Bipolar Integrated Technology.
Taylor has received an Intel Achievement Award for his work on deploying advanced packaging. He has published over 60 papers and holds over 60 patents on integrated circuit design and test. Taylor is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE).
Taylor received his doctorate in computer and systems engineering in 1985 from Rensselaer Polytechnic Institute. His graduate work was completed with the support of a Fellowship from the Fannie and John Hertz Foundation.
Keshavan K TiruvallurIntel Fellow, Client Computing Group
Chief Validation Technologist, Client Research and Development
Keshavan K Tiruvallur (K7) is an Intel Fellow in the Client Computing Group and chief validation technologist for Client Research and Development at Intel Corporation. He is responsible for the strategic direction on post-silicon, device and new experience validation debug process and methods. He is currently leading enhanced platform debug capabilities within Intel as well for Intel's customers in this new era of increased integration and computing experiences.
Tiruvallur joined Intel in 1983 immediately after graduating from college. His first job was computer board test engineer. He has subsequently worked as a BIOS engineer, in firmware, board design, board design evaluation and board test.
Tiruvallur has also worked on microprocessor architecture, taking on such roles as a microcoder, microarchitect and DFx architect. He has developed extensive microcode for the Intel architecture family of products starting with Intel Pentium® Pro, Intel Pentium® II/III family and Intel Pentium® 4 family. Tiruvallur led the microcode team through the Nehalem/Westmere processor family development. He was the lead DFx architect and system debug lead on Nehalem/Westmere family of processors. He has been the IA legacy microarchitect, responsible for maintaining IA legacy features across generations.
Tiruvallur has 14 patents issued or pending, and has won three Intel Achievement Awards.
Tiruvallur earned his bachelor's degree in electrical engineering from B.M. Sreenivasaiah (BMS) College of Engineering, Bangalore, India, in 1978. He earned his master's degree in computer engineering from the University of Memphis in 1983.
Tuyen K. TranIntel Fellow, Technology and Manufacturing Group
Director, Portland Technology Development Defect Metrology
Tuyen K. Tran is an Intel Fellow in the Technology and Manufacturing Group and the director of defect metrology in the Portland Technology Development organization at Intel Corporation. He leads the research, development, integration and transfer of state-of-the-art inspection, imaging and elemental composition-analysis capabilities for Intel's 14-nanometer (14nm) and 10nm process technologies.
Tran joined Intel in 1996 as a process engineer working on defect metrology inspection equipment for Intel's P854 process technology. He was named an engineering technology development manager in 2001 and has since led the development and integration of inspection and imaging capabilities for subsequent process generations of Intel's logic technology evolution.
In 2010, he received an Intel Achievement Award that recognized his contributions to the development of world-leading factory performance, which enabled a two-year development cadence. Tran has also authored or co-authored more than 30 publications in his areas of expertise and holds two provisional patents, 15 invention disclosures and one distinguished invention disclosure.
Before joining Intel, Tran was a staff member at IBM's T.J. Watson Research Center in Yorktown Heights, New York.
Tran holds bachelor's and master's degrees in physics from Rensselaer Polytechnic Institute. He earned a second master's degree in electrical engineering and a Ph.D. in physics, both from Georgia Institute of Technology. He is a member of the American Physical Society and the Optical Society of America.
Richard A. UhligIntel Fellow, Intel Labs
Director, Systems and Software Research
Rich Uhlig is an Intel Fellow and director of Systems and Software Research in Intel Labs, where he leads research efforts in virtualization, software-defined networking, cloud storage, persistent memories, big-data analytics, and programming systems. Uhlig is also the executive sponsor for the Intel Science and Technology Centers (ISTCs) for Cloud Computing (centered at CMU) and Big Data (centered at MIT).
In past work, Uhlig started virtualization efforts within Intel in 1998 and led the definition of multiple generations of virtualization architecture for Intel processors and platforms, known collectively as "Intel Virtualization Technology" (Intel® VT). Intel VT is used today in a variety of settings and applications to improve the utilization, management, availability and security of systems based on Intel architecture.
Prior to joining Intel in 1996, Uhlig held post-doctoral fellowships at the European national research labs of Germany, Greece, and France, where he worked on advancing simulation technology and on architectural support for microkernel operating-system design.
Uhlig has published over 20 technical papers, holds 24 patents, and has received two Intel Achievement Awards for his work on system simulation and Intel® VT. He earned the Ph.D. in Computer Science and Engineering from the University of Michigan in 1995.
Hong WangIntel Fellow, Intel Labs
Director, Microarchitecture Research Lab
Hong Wang is an Intel Fellow and director of the Microarchitecture Research Lab in the Intel Labs organization at Intel Corporation. He manages microarchitecture research for processors and other key intellectual property core designs. Wang's recent work has focused on developing synthesizable, configurable designs that support low-power, energy-efficient system-on-chip (SoC) integration on multiple process technologies. This line of research has led to transformative technologies used in the Intel® Quark™ family of embedded Internet of Things products and Intel's SoFIA family of SoC designs for mobile computing based on Intel® Atom™ processors.
Wang joined Intel in 1995, initially contributing to the development of cycle-accurate CPU simulators and fast platform-level simulators for multiple Intel processors. Subsequently, he led research in developing helper threading techniques for prescient memory prefetching, and he spearheaded efforts to define novel architecture extensions to enable shared virtual memory user-level multithreading on heterogeneous chip multiprocessors. Wang also led efforts to make multiple CPU designs ready for field-programmable gate array (FPGA) emulation to support architecture exploration, design validation and early software enabling.
Intel has honored Wang with three Intel Achievement Awards — in 1999 for his work on platform-level software simulation; in 2008 for making Atom processors ready for the FPGA emulation; and in 2011 for developing the sub-Atom core inside the Quark products, thereby creating a foundation for Intel's low-end processor roadmap. He is also a recipient of the 2011 Mahboob Khan Outstanding Industry Liaison Award from the Semiconductor Research Corporation.
Before joining Intel, Wang was a hardware engineer at American Power Conversion Corporation.
Wang has published more than 50 technical papers and has been granted 145 patents, with another 80 patents pending, in areas including processor architecture and microarchitecture.
Wang holds a bachelor's degree in computer engineering from the Harbin Institute of Technology in China and a Ph.D. in electrical engineering from the University of Rhode Island.
Geng WuIntel Fellow, Platform Engineering Group
Chief Technologist, Wireless Standards
Geng Wu is an Intel Fellow and chief technologist for wireless standards in the Platform Engineering Group at Intel Corporation. Wu leads Intel's fifth-generation (5G) wireless standards development and ecosystem collaboration. He also heads Intel's delegation to the 3rd Generation Partnership Project (3GPP), an industry coalition dedicated to global wireless communication standards.
Wu joined Intel in 2009 as a technology advisor and contributor to Intel's Cloud-RAN and machine-to-machine platform and technology development. In 2010, he was named chief architect for wireless standards development, with an emphasis on 3GPP LTE and LTE-A development. Before assuming his current role, he led the development of 5G air interface and network standards at Intel, working with internal and external colleagues on the next generation of computing and communication technologies.
Wu has more than 20 years of research and development experience in the wireless industry. He has contributed extensively to global 2G CDMA, 3G 1xRTT, UMTS, HSPA and 4G WiMAX, LTE radio interface and network architecture design and development. His current research interests include mobile computing and communication platforms, heterogeneous networks, channel modeling, next-generation air interface technologies, and cross-layer optimization for mobile services and applications.
Before joining Intel, Wu served as director of wireless architecture and standards at Nortel Networks, where he was responsible for system performance, standards research, and technology development in 3GPP2, 3GPP, IEEE and WiMAX. In 2004, Nortel honored him with its Corporate Technology Award of Excellence.
Wu received his bachelor's degree in electrical engineering from Tianjin University in Tianjin, China; and his Ph.D. in telecommunications from Université Laval in Québec, Canada. He has been issued more than 30 U.S. patents, with many additional patents pending. He has also authored or co-authored more than 40 research publications in the field of mobile wireless communications and networking.
Kevin X. ZhangVice President, Technology and Manufacturing Group
Director, Advanced Design, Logic Technology Development
Kevin Zhang is an Intel Fellow and vice president in the Technology and Manufacturing Group at Intel Corporation and director of advanced design in logic technology development. He is responsible for advanced circuit technology development for the company's future products. Zhang oversees the development of process design rules, digital circuit libraries, key analog and mixed-signal circuits, high-speed I/Os and embedded memories. He is also responsible for delivering the first technology vehicles for each new logic technology development at Intel.
Since joining Intel in 1997, Zhang has held several technical and management positions. Prior to his current role, he led Intel's embedded memory technology development from 90-nanometer (90nm) to 22nm generations. In 2005, Zhang was appointed an Intel Fellow for his technical leadership in memory technology. He has led his teams to win five Intel Achievement Awards in the area of advanced memory and digital circuit technology development.
Zhang has published more than 55 papers at international conferences and in technical journals and is the editor of Embedded Memory for Nano-Scale VLSIs, published by Springer in 2009. He holds more than 45 U.S. patents in the field of integrated circuit technology. Zhang chairs the memory subcommittee of the International Solid-State Circuits Conference (ISSCC) and is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE).
Zhang received his bachelor's degree from Tsinghua University in Beijing in 1987 and his Ph.D. from Duke University in 1994, both in electrical engineering.