|View Bio Close BioBoris A. BabayanIntel Fellow, Software and Services Group|
Boris Babayan is an Intel Fellow and director of Architecture for the Software and Services Group at Intel Corporation. He leads worldwide efforts related to compiler technologies for Intel server products, technologies that enable applications to run on multiple computer architectures without recompiling, and helping to develop Intel security technologies. He will also be a key Intel representative to the leading Russia Academies and Universities, working to attract top talent to Intel sites located in Moscow, Nizhniy and Novosibirsk.
Babayan joined Intel in August of 2004. Prior to coming to Intel, he held numerous positions, including director of the Institute of Microprocessor Computer Systems for the Russian Academy of Science, chairman of Elbrus International, chief technological officer at the Moscow Center for SPARC Technologies and director of the Institute of Computer Technologies. From 1956 to 1996, Babayan worked at the Institute of Precise Mechanics and Computer Technology, eventually becoming chief of the hardware and software division. He completed his Ph.D. in 1964 and his doctorate of science in 1971. Babayan served as professor and chair of Computer Science at the Moscow Institute of Physics and Technology from 1996 to 2004.
Babayan has been a corresponding member of the Russian Academy of Science since 1984, has served as chairman of the Academic Council at the Institute of Microprocessor Computer Systems, RAS, and chairman of the dissertation council for awarding Ph.D. and Doctorate of Science Degrees, IMCS RAS. He is a member of the State Committee for State Prize Award of Russian Federation. He has served as a member of editorial boards for a number of technical journals, including deputy editor-in-chief of the Information Technologies and Computer Systems journal for the Russian Academy of Science.
Babayan's awards include the State Prize award for development and implementation of complex equipment for CAD, manufacturing and control of complex electronics in 1974; the Lenin Prize award for development and implementation of multiprocessor computer system Elbrus 2 in 1987; the Order of the Red Banner of Labor in1972; the Order of the October Revolution for design and development of Elbrus 1 computer in1982; and the Medal of Honor for design and development of Elbrus 90micro computer in 2000. He has published numerous book and papers on computer architecture. He was born December 20, 1933.
|View Bio Close BioGenevieve BellIntel Fellow, Intel Labs|
Director, User Experience Research
Dr. Genevieve Bell is an anthropologist and researcher with 15 years of experience driving innovation in the high-tech industry. As the director of User Experience Research in Intel Labs, Bell leads a team of social scientists, interaction designers, human factors engineers and computer scientists. This organization researches new computing experiences that are centered around people's needs and desires. This foundationally shapes and then helps to create new Intel technologies and products. In this team and her prior roles, Bell has fundamentally altered the way Intel envisions and plans its products so that they are centered on people's needs rather than simply silicon capabilities.
In addition to leading this increasingly important area at Intel, Bell is an accomplished industry commentator on the intersection of culture and technology and has been extensively featured in publications that include Wired, Forbes, The Atlantic, Fast Company and the Wall Street Journal. She is a frequent public speaker and panelist at technology conferences worldwide, sharing myriad insights gained from her extensive international field work and research. In 2010, Bell was named one of Fast Company's inaugural "100 Most Creative People in Business." Bell is a passionate advocate for the advancement of women in technology and in 2012 was inducted into the Women In Technology International (WITI) Hall of Fame, as well being honored by the Anita Borg Institute as the 2013 Woman of Vision for Leadership. Her first book, "Divining the Digital Future: Mess and Mythology in Ubiquitous Computing," was co-written with Prof. Paul Dourish of the University of California at Irvine and released in April 2011. Bell is also the recipient of several patents for consumer electronics innovations.
A native of Australia, Bell moved to the United States for her undergraduate studies and graduated from Bryn Mawr in 1990 with a bachelor's degree in anthropology. She then earned a master's degree and a doctorate in cultural anthropology from Stanford University where she also taught as an acting lecturer in the Department of Anthropology from 1996-1998. With a father who was an engineer and a mother who was an anthropologist, perhaps Bell was fated to ultimately work for a technology company, joining Intel in 1998.
|View Bio Close BioAjay V. BhattIntel Fellow, Platform Engineering Group|
Chief Platform Architect, PC Client Group
Ajay Bhatt is an Intel Fellow for the Platform Engineering Group and chief platform architect for the PC Client Group at Intel Corporation. Currently, Bhatt is leading an architectural effort to transform the PC by working with key internal and external technology partners to develop future platform architectures and technologies. He also collaborates with key business and planning groups to position Intel at the forefront of future client platform innovation by setting company- and industry-wide impact strategies.
Bhatt is an industry-recognized technical expert in the area of Platform Architecture and I/O technologies. Bhatt joined Intel in 1990. At Intel, he has been the chief architect and co-inventor of broadly adopted technologies such as USB, Accelerated Graphics Port, PCI Express, platform power management architecture and various personal computer enhancements. The technologies he has helped developed have had profound impact on the computer industry. Bhatt currently holds 32 patents in the area of Platform architecture and I/O technologies several in various stages of filing.
Bhatt earned his master's degree from The City University of New York and currently holds 32 patents with several in various stages of filing. Bhatt, who is based in Hillsboro, Ore., is invited worldwide to give technical talks at leading universities and industry groups. His recognitions include being named one of "The Most Influential Global Indians", The Light of India Award 2012, for his contributions in advancement of science and technology, The Asian Award 2013 for outstanding achievement in Science and technology and EU Inventor award 2013 for his contributions to the development of USB.
|View Bio Close BioDavid R. BlytheIntel Fellow, Platform Engineering Group|
Chief Graphics Software Architect, Visual and Parallel Computing Group
David Blythe is an Intel Fellow for the Platform Engineering Group and chief graphics software architect for the Visual and Parallel Computing Group at Intel Corporation. He leads the development of advanced features and application programming interfaces (APIs) for Intel's processor graphics products, as well as the software architecture for Intel's processor graphics and Xeon Phi architectures.
Before joining Intel in 2010, Blythe spent 7 years at Microsoft Corporation, most recently as a partner software architect with responsibility for the architecture of Windows graphics APIs and component implementations. Earlier in his career, he was a senior system architect and co-founder of BroadOn Communications Corp. and a chief engineer at Silicon Graphics Inc.
A member of the Institute of Electrical and Electronics Engineers (IEEE) and the Association for Computing Machinery (ACM), Blythe has authored or co-authored more than 15 technical papers published in industry journals. He has been granted 15 patents, with another five patents pending, in the field of computer graphics.
Blythe holds a bachelor's and a master's degree in computer science, both from the University of Toronto.
|View Bio Close BioZdravko BoosIntel Fellow, Platform Engineering Group|
Radio Smartphone System Engineering
Zdravko Boos is an Intel Fellow and an expert in Radio Smartphone System Engineering for the Platform Engineering Group at Intel Corporation. He is responsible for the development of advanced digital cellular transceiver concepts suitable for System-on-Chip (SoC) integration.
Previously with Siemens Semiconductors in 1998 and later in 1999 with spin-off semiconductor operations at Infineon, Boos worked on RF CMOS IP development, where he developed solutions for the world's first 3G CMOS transceiver used widely in mobile phones. With increased demand for highly integrated multimode, multiband mobile phones, he led successful pre-development of a single chain transmitter which enabled reduction of power amplifiers from 4:1, at the same time providing unique advantages in power consumption, chip area, shrink ability and BOM.
Prior to Siemens, Boos was with Philips Consumer Electronics Eindhoven, where he developed DAB front-ends for reference DAB452 and DAB752 receivers. Before Philips he was with Radio Industry Zagreb, developing frequency synthesizers and UHF transmitters.
Boos holds 15 US patents, he has managed the European Information Societies Technology Program, "Design Methodology and Implementation of a 3rd Generation W-CDMA Transceiver using Deep Submicron CMOS Technologies," and he has organized and managed technical co-operations with a number of universities: University of Aachen, University of California, Berkeley, University of Chalmers, ETH Zuerich, University of Erlangen, JKU Linz, TU Munich, University of Stuttgart, University of Tampere, and University of Udine where more than 20 Ph.D students earned their promotions.
Boos received his bachelor's degree in electrical engineering from University of Zagreb in 1982. He also earned his master's degree from the Eindhoven International University in 1991.
|View Bio Close BioShekhar Y. BorkarIntel Fellow, Data Center Group|
Director, Extreme-scale Technologies
Shekhar Y. Borkar is an Intel Fellow and director of Extreme-scale Technologies for the Data Center Group at Intel Corporation. Borkar is responsible for directing extreme-scale research in technologies for Intel's future microprocessors.
Borkar joined Intel in 1981. He worked on the design of the 8051 family of microcontrollers, iWarp multicomputer and high-speed signaling technology for Intel supercomputers. Borkar is an adjunct member of the faculty of the Oregon Graduate Institute. He has published over 100 articles and holds 50 patents.
Borkar was born in Mumbai, India. He received a master's degree in Electrical Engineering from the University of Notre Dame in 1981, and a master and bachelor degrees in Physics from the University of Bombay in 1979.
|View Bio Close BioFayé BriggsIntel Fellow, Data Center Group|
Chief Server Architect
Fayé Briggs is an Intel Fellow and chief server architect for the Data Center Group at Intel Corporation. He is responsible for ensuring that Intel's multi-core and many-core-based server platform architectures for the data center, achieve best-in-class attributes, such as performance, reliability, availability, serviceability, power-efficiency, and security in each server market segment .
Briggs has had a leadership role in developing multiple generations of innovative multiprocessor server platforms and chipset designs, including all current front side bus-based Intel® Xeon® dual- and multi-processor server chipsets and platform architectures. He conceptualized the first Intel point-to-point coherent scalability port for 2P-16P scalable architecture family of 870 server chipsets for Itanium® processor-based and Intel Xeon processor-based servers and led development of the devices. Briggs served as the Intel Fellow-In-Residence for China during 2011-2012.
Prior to joining Intel in 1997, Briggs held various positions at Sun Microsystems including serving as a co-architect of Sun's original SPARC processor. He was also a co-founder and CTO of Axil Computers, where he led the development of chipsets, boards and systems for more than 30 servers, storage and workstation products. Briggs also served as a tenured associate professor at Rice University and as a faculty member at Purdue University, both in electrical and computer engineering.
Briggs has published numerous technical papers on processor and multiprocessor architectures and micro-architectures, memory ordering, cache coherence and system performance. He is the co-author of the McGraw-Hill-published textbook "Computer Architecture and Parallel Processing." Briggs has been awarded four patents and received an Intel Achievement Award for the successful definition and execution of Intel's first quad core products.
Briggs received his bachelor's degree in engineering from Ahmadu Bello University, Nigeria. He received his master's degree in electrical engineering from Stanford University, and his doctorate in electrical and computer engineering from the University of Illinois, Urbana-Champaign.
|View Bio Close BioDouglas M. CarmeanIntel Fellow, Intel Labs|
Director, Immersive Computing
Doug Carmean is an Intel Fellow and director of Immersive Computing for Intel Corporation.
Since joining Intel in 1989, he has held several key roles and provided leadership in Intel's microprocessor architecture development and product roadmap. As Nehalem's first chief architect, a next-generation x86 flagship processor, he led the team during the early phases of architecture definition. Prior to this position, he was a principal architect for the Pentium 4 processor where he completed the memory cluster and power architecture definition including algorithms, structures and overall functionality.
Carmean holds more than 20 patents and many pending in processor architecture and implementation, memory subsystems and low power design. He has published more than a dozen technical papers and he has received the Intel Achievement Award three times.
Carmean earned his bachelor's degree in electrical engineering from Oregon State University in 1985.
|View Bio Close BioVivek K. DeIntel Fellow, Intel Labs|
Director, Circuit Technology Research
Vivek K. De is an Intel Fellow and director of Circuit Technology Research in Intel Labs.
De joined Intel in 1996 as a staff engineer in Intel's Circuits Research Lab (CRL). Since that time he has led research teams in CRL focused on developing advanced circuits and design techniques for low-power and high-performance processors. In his current role as director of CRL in the Circuits and Systems Research group of Intel Labs, De provides strategic direction for future circuit technologies and is responsible for aligning Intel's circuit research with technology scaling challenges.
De has published more than 200 technical papers and holds 185 patents with 28 more patents filed (pending). He received an Intel Achievement Award for his contributions to a novel integrated voltage regulator technology. He is a Fellow of the IEEE.
Prior to joining Intel, De was engaged in semiconductor devices and circuits research at Rensselaer Polytechnic Institute and Georgia Institute of Technology, and was a visiting researcher at Texas Instruments.
De received his bachelor's degree in electrical engineering from the Indian Institute of Technology in Madras, India in 1985 and his master's degree in electrical engineering from Duke University in 1986. He received a Ph.D. in electrical engineering from Rensselaer Polytechnic Institute in 1992.
|View Bio Close BioEric DishmanIntel Fellow, Data Center Group|
General Manager, Health and Life Sciences
Eric Dishman is an Intel Fellow and general manager of the Health and Life Sciences for the Data Center Group at Intel Corporation. He is responsible for driving Intel's cross-business strategy, R&D, product, and policy initiatives for health and life science solutions. His organization focuses on growth opportunities for Intel in health IT, genomics and personalized medicine, consumer wellness, and care coordination technologies in more than a dozen countries.
Dishman is widely recognized as a global leader in healthcare innovation with specific expertise in home and community-based technologies and services for chronic disease management and independent living. He is also known for pioneering innovation techniques that incorporate anthropology, ethnography, and other social science methods into the design and development of new technologies. He and his team's work have been featured in publications including the New York Times, Washington Post, Business Week, and USA Today. The Wall Street Journal named him one of "12 People Who Are Changing Your Retirement."
An internationally renowned speaker, Dishman has delivered hundreds of prominent keynotes on healthcare reform and innovation around the globe, from the Consumer Electronics Show to TED to the White House Conference on Aging to the World Health Organization. He has published dozens of articles on personal health technologies and co-authored many government reports on health information technologies and reform.
Dishman co-founded some of the world's largest research and policy organizations devoted to advancing the cause of independent living, including the Technology Research for Independent Living (TRIL) Centre, the Center for Aging Services Technologies (CAST), the Everyday Technologies for Alzheimer's Care (ETAC) program, and the Oregon Center for Aging & Technology (ORCATECH). Dishman has received numerous awards for his work in helping to shape the future of health care.
Social Networks: Dishman writes about his vision, experiences, and concerns on healthcare IT and policy issues, especially around the growth of personal health technologies for the home at:
|View Bio Close BioMark S. DoranIntel Fellow, Software and Services Group|
Chief Platform Software Architect, System Software Division
Mark Doran is an Intel Fellow and the chief platform software architect within the System Software Division for the Software and Services Group at Intel Corporation. As lead architect for the Unified Extensible Firmware Interface (UEFI) program and the company's implementation of UEFI, codenamed "Tiano," he develops industry standards-based firmware for Intel architecture systems. Doran also serves as president of the UEFI Forum, a non-profit trade organization that develops the primary de jure industry standards for platform firmware.
Before assuming his current position at Intel, Doran was the program manager for the Intel boot initiative. That initiative, which involved defining a boot solution for Intel Itanium processor-based platforms, led to the Extensible Firmware Interface (EFI). Earlier in his Intel career, Doran served as manager of the Applications Solution Center, and as the developer and author of the Multiprocessor Specification (MPS), the first recipe for commodity multi-CPU, PC-compatible computers and operating systems. He joined Intel in 1994 as a software engineer for UNIX operating system development. Before coming to Intel, he was with UNIX International and served as a consultant in open systems development for The Instruction Set Ltd. in London.
Doran is the author of two books and numerous articles published in technical journals. He holds 19 patents in the field of platform firmware and system boot architecture, with another four patents pending, and he is a four-time winner of the Intel Achievement Award for technological innovation and his contributions to firmware engineering.
Doran earned a bachelor's degree in computer science with electronic engineering from University College, London University, in the United Kingdom.
|View Bio Close BioPradeep K. DubeyIntel Fellow, Intel Labs|
Director, Parallel Computing Lab
Pradeep Dubey is an Intel Fellow and director of the Parallel Computing Lab, a part of the Intel Labs organization at Intel Corporation. Since 2003, he has led a team of top researchers focused on state-of-the-art research in highly parallel computing. Dubey and his team are charged with defining computer architectures that can efficiently handle new compute-intensive and data-intensive application paradigms for future computing environments, and deriving product differentiation opportunities for Intel multi-core and many-core platforms.
Dubey previously worked at Intel from 1984 to 1991. Before rejoining the company in 2003, he had served as a research staff member at IBM's T.J. Watson Research Center from 1991 to 2001. While there, he was one of the principal architects of the AltiVec multimedia extension to the Power PC architecture.
Throughout his career, Dubey has made significant contributions to the design, architecture and application performance of various microprocessors, including the IBM Power PC, the Intel386™, Intel486™, Intel® Pentium® and Intel Xeon® processors, and Intel's new Many Integrated Core (MIC) line of processors.
He holds more than 30 patents and has published more than 50 peer-reviewed technical papers. In 2012, Dubey was honored with an Intel Achievement Award for breakthroughs in parallel computing research.
Dubey earned a bachelor's degree in electronics and communication engineering from Birla Institute of Technology, India; a master's degree in electrical engineering from the University of Massachusetts at Amherst; and a Ph.D. in electrical engineering from Purdue University. He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2001 for his contributions to computer architecture supporting multimedia processing.
|View Bio Close BioJoel S. EmerIntel Fellow, Data Center Group|
Director, Microarchitecture Research
Joel S. Emer is an Intel Fellow and director of Microarchitecture Research for the Data Center Group at Intel Corporation.
Emer joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel. Prior to joining Intel, Emer was a Compaq Fellow and Director of Alpha Architecture Research, where he led research efforts for future processors for Compaq's 64-bit family of servers.
With over 25 years of combined service to Compaq and Digital Equipment Corporation, Emer has held various research and advanced development positions investigating processor microarchitecture designs and developing performance modeling and evaluation techniques. Emer is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. More recently, he has been recognized for his contributions in the advancement of simultaneous multithreading technology. He holds 15 patents and has published more than 30 papers.
Emer received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. Emer earned a doctorate in electrical engineering from the University of Illinois in 1979.
|View Bio Close BioAlbert FazioIntel Fellow, Technology and Manufacturing Group|
Director, Memory Technology Development
Albert Fazio is an Intel Fellow and Director of Memory Technology Development in the Technology and Manufacturing Group. In his current position, Fazio is responsible for exploring and developing flash memory and multi-level cell memory technologies as well as novel memory technology ideas.
Since joining Intel in 1982, Fazio has been involved in various engineering roles in memory development programs including SRAM, EPROM, E2PROM, NVRAM and Flash Memories. His technical contributions and leadership have helped pioneer new capabilities in the area of Flash, Strata-Flash, and Flash and logic combinations, providing cost and functionality advantages to Intel products.
Fazio's technical papers have been published in several publications and at international technical conferences. He received outstanding paper awards at the IEEE International Reliability Physics Symposium and IEEE International Solid-State Circuits Conference. Fazio holds 24 patents and has received three Intel Achievement Awards. He frequently serves as a panelist on international memory panels and gives technical seminars and talks to the industry and universities. He previously served as Technical and General Chairman of the IEEE Non-Volatile Semiconductor Memory Workshop.
Fazio received his bachelor's of science in Physics from The State University of New York at Stony Brook in 1982. He was born in New York City in 1961.
|View Bio Close BioTryggve FossumIntel Fellow, Data Center Group|
Director, Scalable Computer Architecture
Tryggve Fossum is an Intel Fellow and director of Scalable Computer Architecture for the Data Center Group at Intel Corporation. He leads a research group of engineers looking for how to best scale chip designs to support many cores on die, and to scale systems to thousands of nodes in the network. The group works with product development teams to address challenges with memory bandwidth, cache coherence, on-die interconnect, network interface, router architecture and network topology in distributed memory systems. All of this while dealing with error rates and power constraints. In recent years, Tryggve was the lead architect for an innovative Itanium server chip, and a pioneering Xeon server chip. He received an Intel Achievement award for his work on the ring interconnect for multi core architectures.
Fossum joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel.
Prior to joining Intel, Fossum held a variety of positions during 28 years of combined service to Compaq and Digital Equipment Corporation. Since 1998, he served as a Compaq Fellow and was lead architect for future versions of the Alpha microprocessor. From 1991 to 1998, Fossum led a team conducting processor and compiler technology research. Prior to this, he was a consulting engineer and helped design several VAX processors for Digital.
Fossum received a Cand Mag degree in Science from the University of Oslo in 1968.He earned his doctorate and master's degree in mathematics from the University of Illinois in 1972 and 1970, respectively. Fossum completed a post-doctorate program at the University of Illinois in 1973.
Fossum holds 37 patents on various aspects of computer design, including floating point, error handling, vector processing, multithreading and cache organization technologies.
|View Bio Close BioAlan GaraIntel Fellow, Data Center Group|
Chief Architect, Exascale Systems
Alan Gara is an Intel Fellow and chief architect for Exascale Systems for the Data Center Group at Intel Corporation.
Prior to joining Intel in 2011, Dr. Gara was in IBM Watson research, where he was chief architect for three generations of Blue Gene machines. The first generation Blue Gene/L machine was number one on the Top500 list from November 2004 to November 2007. Dr. Gara received a second Gordon Bell award for QCD calculations done on the Blue Gene machine in 2006. Innovations in the Blue Gene architecture have resulted in his more than 70 patents. Dr. Gara was promoted to IBM fellow in 2007. President Obama awarded IBM with the National Medal of Technology and Innovation for Blue Gene in 2009.
Gara previously joined Columbia University in 1992, where he became a member of the E690 experimental group at Fermilab. This was followed by work at the Large Hadron Collider at CERN. In parallel with this experimental physics work, he collaborated with the Columbia University theory group lead by Professor Norman Christ. This group designed and built the QCDSP supercomputer, optimized for Quantum Chromodynamics (QCD) calculations. Dr. Gara was awarded his first Gordon Bell award for this work in 1998.
Gara received his PhD in physics from the University of Wisconsin, Madison in 1987 for his work calculating the meson mass spectra utilizing a relativistic Bethe-Salpeter approach.
|View Bio Close BioTahir GhaniIntel Fellow, Technology and Manufacturing Group,|
Portland Technology Development
Director, Transistor Technology and Integration
Tahir Ghani is an Intel Fellow and director of transistor technology and integration for the Technology and Manufacturing Group. He is currently leading the Pathfinding team responsible for transistor design and front-end processor integration for Intel's 22nm CMOS logic technology node.
Since joining Intel in 1994, Ghani has played a key role in developing world-class CMOS logic technologies. He has led the research and development teams responsible for introducing some of the most important innovations in transistor technology and implementing these into mainstream CMOS manufacturing. Ghani co-led the team responsible for developing industry-first HiK/Metal Gate CMOS transistor technology for Intel's 45nm technology node. Prior to that, he led the integration team which was responsible for developing industry-first uniaxially strained silicon transistors for Intel's 90 CMOS node. Ghani and co-workers were the first to publish a novel epitaxial SiGe source drain transistor at IEDM 2003 which introduced high levels of strain for significant PMOS mobility enhancement. As a member of the 22nm CMOS Pathfinding team at Intel, Ghani is currently leading 22nm CMOS transistor technology research and development.
Ghani has received two Intel Achievement Awards. The first, awarded in 1996, was for his role in developing leading-edge 0.25um CMOS transistor technology. He received the second in 2003 for developing uniaxially strained silicon transistor technology for Intel's 90nm logic technology node. He has published more than 30 technical papers, many of which have been presented at leading technical conferences.
Ghani received his B.S. in electrical engineering at the University of Engineering and Technology in Lahore, Pakistan in 1984 and his Ph.D. in electrical engineering at Stanford University in 1994. He is a Fellow of IEEE.
|View Bio Close BioKnut S. GrimsrudIntel Fellow, Technology and Manufacturing Group|
Director, Storage Architecture
Knut S. Grimsrud leads a research and development group responsible for mainstream and consumer storage interface definition and enabling. He is also responsible for developing new mainstream storage innovations for Intel platforms. Grimsrud and his team currently manage definition and ongoing evolution of the Serial ATA interface as well as the definition and industry enabling for the CE-ATA interface. He is also researching new applications of Flash in Intel platforms.
Grimsrud joined Intel in 1993 as a hardware engineer in the Intel Architecture Labs where his primary focus was on improving the storage performance of Intel's entry into the standard high-volume server segment. His focus transitioned to mainstream storage optimization techniques in the Platform Architecture Labs where his contributions included disk reorganization techniques for improved application launch performance. Grimsrud then drove definition of the Serial ATA disk drive interface standard and its subsequent evolutions and enhancements, which continues today under his group in the Storage Technologies Group.
Grimsrud received his bachelor's degree in electrical engineering in 1988, his master's degree in electrical and computer engineering in 1989 and his Ph.D in 1993, all from Brigham Young University. Grimsrud holds 23 U.S. patents and has received three Intel Achievement Awards and a Lifetime Achievement Award from Intel IDF. He serves as chairman of the board of directors for the Serial ATA International Organization and chairman of the steering committee of the CE-ATA Working Group.
|View Bio Close BioFrank T. HadyIntel Fellow, Technology and Manufacturing Group|
Director, Non-Volatile Memory Platform Architecture
Frank T. Hady is an Intel Fellow and director of non-volatile memory platform architecture in Intel Corporation's Technology and Manufacturing Group. He leads research and design of platform innovations for non-volatile memory as the architect of high-performance Intel solid-state drives and as manager of the research team identifying and prototyping platform-level innovations to determine the best uses for these devices.
Hady joined Intel in 1995 as a hardware engineer in the Platform Architecture Labs and has focused on platform I/O innovation throughout his Intel career. He served as Intel's chief I/O architect and has been a leader of cross-company research into shared storage architectures. Hady's research into tightly coupled heterogeneous processors led to the product line formerly codenamed "Tolapai" and Intel QuickAssist technology. Methodologies, tools and standards invented by Hady and his team have improved the way Intel and the industry measure performance, resulting in significant chipset, network processor, I/O device and network storage enhancements.
Before joining Intel, Hady was a research scientist at the Supercomputing Research Center, where he built parallel computers and researched network improvements.
Hady has authored or co-authored more than 30 published papers on topics related to networking, storage and I/O innovation. He holds 22 U.S. patents, with more patents pending, spanning heterogeneous multi-processor architecture, performance measurement techniques, networking and storage and platform I/O architectures.
A senior member of the Institute of Electrical and Electronics Engineers (IEEE), Hady received his bachelor's and master's degrees in electrical engineering from the University of Virginia, and his Ph.D. in electrical engineering from the University of Maryland.
|View Bio Close BioPer HammarlundIntel Fellow, Platform Engineering Group|
Chief System-on-Chip (SoC) Architect, Next-Generation Processor Chief Architect
Per Hammarlund is an Intel Fellow, chief System-on-a-Chip (SoC) architect, and Next-Generation Processor chief architect for the Platform Engineering Group at Intel Corporation. As chief SoC architect at Intel Corporation, Hammarlund is responsible for PEG products spanning from phone to server. He is also the chief architect for Intel's next-generation family of products targeted at PC clients.
Hammarlund joined Intel in 1997, contributing to performance modeling and microarchitecture development of the Intel® Pentium® 4 processor architecture. Subsequently, he served as one of the lead architects for the Intel processor family formerly codenamed "Nehalem," with specific responsibility for the server segment.
While still in high school, Hammarlund began building computers from microcontrollers and discrete logic chips. During his university years, he worked on embedded and "real-time" computers. He also worked at the Center for Parallel Computers at the Royal Institute of Technology.
Hammarlund has received two Intel Achievement Awards, the first in 2002 for inventing and implementing Intel® Hyper-Threading Technology, and a second in 2008 for architecture and circuit innovations on Nehalem. He holds 47 patents in computer architecture.
Hammarlund holds a master's degree in computer science and a Ph.D. in computer science and engineering, both from the Royal Institute of Technology in Stockholm, Sweden.
|View Bio Close BioJames P. HeldIntel Fellow, Intel Labs|
Director, Microprocessor and Programming Research
As director of Microprocessor and Programming Research, Jim Held leads a team conducting research in microarchitecture, parallel computing and programming systems to develop key technologies for future microprocessors and platforms.
Since joining Intel in 1990, Held has served in a variety of positions working on computer supported collaboration technology and Intel Native Signal Processing (NSP) infrastructure. He served as staff principal architect in the Media and Interconnect Technology Lab in IAL and as the Lab Director in CTG, managing the Volume Platforms Lab. As a Senior Principal Engineer in the Microprocessor Technology Lab, he conducted research on extensible processor architecture, multi-core processor architecture and helped develop Intel's virtualization technology strategy. From 2005-2011 he led a virtual team of senior architects conducting Intel Lab's Tera-Scale Computing Research.
Before coming to Intel, Held worked in research and teaching capacities in the Medical School and Department of Computer Science at the University of Minnesota. He is a Member of the IEEE Computer Society and the Association for Computer Machinery (ACM).
Held earned a B.S. in Chemical Engineering in 1972 and an M.S. (1984) and Ph.D. (1988) in Computer and Information Science, all from the University of Minnesota.
|View Bio Close BioBruce HornIntel Fellow, New Devices Group|
Chief Scientist, Smart Device Innovation
Bruce Horn is an Intel Fellow and Chief Scientist for Smart Device Innovation in the New Devices Group (NDG) at Intel Corporation. He is responsible for the vision and architecture of intelligent personal devices and systems within NDG.
Previous to joining Intel, Dr. Horn was Principal Research Software Development Engineer at Microsoft Corp. where he worked on the creation and deployment of Natural Language systems for Bing, Microsoft's search engine. Before joining Microsoft, he was at Powerset Inc. where he was responsible for the computational infrastructure of the Powerset Natural Language Search System.
Horn is most widely known for his work at Apple, where he created and developed the Macintosh Finder - the first widely-used desktop graphical user interface. He began his career as a member of the Learning Research Group at the Xerox Palo Alto Research Center, where he contributed to several implementations of the Smalltalk virtual machine.
Horn earned a B.S. In Mathematical Sciences from Stanford University in 1981, and an M.S. And Ph.D. In Computer Science from Carnegie-Mellon University in 1994.
|View Bio Close BioChia-Hong JanIntel Fellow, Technology and Manufacturing Group|
Director, System-on-Chip (SoC) Technology Integration
Chia-Hong Jan is an Intel Fellow and director of system-on-chip (SoC) technology integration for the Technology and Manufacturing Group. In this role, Jan manages 32nm and 22nm process technologies for all of Intel Corporation's SoC products, including ultra low power mobile Internet devices, netbook processors, consumer electronics products, embedded products, wireless communication applications and chipset/graphic processors.
Since joining Intel in 1991, Jan has held a number of technical and management positions in Portland Technology Development for 0.8um, 0.55µm, 0.35µm, 0.25µm, 0.18µm, 0.13µm, 90nm, 65nm, 45nm, 32nm and now 22nm advanced CMOS technology development. He was the rapid thermal processing (RTP) and advanced silicon deposition (ASD) group leader, working on the development of novel salicide technology, advanced gate oxide processes, source/drain junction engineering and epi SiGe technology for strained silicon. He led the team that spearheaded the integration of new salicide materials, including titanium (0.55µm), cobalt (0.18µm) and nickel into the basic logic CMOS process. He was the 90nm interconnect integration manager, and his team was the first in the industry to successfully integrate low-k ILD materials for high performance microprocessors. He was also the program manager for the 65nm low-power chipset process technology and 45nm SoC process technology for Intel® Atom™ processor –based low-power products, which were the first in industry to deploy the innovative high-k/metal gate technology on SoC.
Jan holds 37 U.S. patents in the fields of semiconductor manufacturing process and integration. He has published more than 40 technical papers related to CMOS processing technology. Jan has received three Intel Achievement Awards and is the recipient of the 2008 Distinguished Achievement Award of the College of Engineering at the University of Wisconsin-Madison.
Jan received his bachelor's degree in chemical engineering from National Taiwan University in 1982. He also earned his MBA from National Taiwan University in 1986. He then earned his master's degree and Ph.D. in materials science from the University of Wisconsin-Madison in 1988 and 1991, respectively.
|View Bio Close BioLink C. JawIntel Fellow, Internet of Things Solutions Group|
Link Jaw is an Intel Fellow focusing on analytics and predictive modeling for Intel Corporation. As part of the Internet-of-Things Solutions Group (ISG), he works to enhance edge-to-cloud compute solutions with an emphasis on data analytics and distributed intelligence; he also provides thought leadership in IoT architecture and applications.
Jaw has 30 years of experience in applying modeling, simulation, and data analytics to the control of dynamic systems and predictive maintenance. Before joining Intel, he was the founder and president of Scientific Monitoring, Inc. His other industry experience includes Alliedsignal Aerospace, Link Flight Simulation, and FlightSafety Simulation.
Jaw is the principal investigator for more than 50 R&D projects and holds 11 U.S. patents. He has authored or co-authored more than 30 peer-reviewed papers. He is also the primary author of the book on "Aircraft Engine Controls: Design, System Analysis, and Health Monitoring," published by AIAA Education Series in August 2009. The book was sponsored by the U.S. Air Force and NASA with the objective of preserving the previously scattered and endangered knowledge in aircraft engine control. This book was also published in Chinese language in March 2011 under the sponsorship of AVIC.
Jaw holds a Ph.D. degree in Aeronautics & Astronautics from Stanford University, an M.S. degree in Aerospace Engineering from the University of Michigan. He also completed EMBA short courses at Dartmouth College's Tuck School of Business Administration.
|View Bio Close BioHong JiangIntel Fellow, Platform Engineering Group|
Chief Media Architect and Director, Visual and Parallel Computing Group Media Architecture Team
Hong Jiang is an Intel Fellow and the chief media architect for the Platform Engineering Group and director of the Visual and Parallel Computing Group's Media Architecture Team at Intel Corporation. He leads the media architecture of processor graphics and its derivatives, including the definition of media hardware and software assets and the group's technology roadmap. As chief media architect - a position he has held since 2002 - Jiang earned recognition for co-inventing the programmable Intel graphics architecture that has powered all Intel client PCs since 2006.
In a previous role as a platform architect at Intel, Jiang contributed to and co-edited key interconnect and video-coding standards. Earlier, as a video architect, he led video decoder and video capture hardware and software definition and implementation for chipset graphics products. Jiang joined Intel in 1996 in the then-newly formed graphics operation in Intel's PCI Component Division.
Jiang has more than 20 journal and conference publications to his name, and he holds 38 issued patents and 44 pending patents in the fields of imaging and visual computing, graphics and media architecture, video compression, video processing, inter-chip communication, computer system architecture and processor architecture. He was honored with an Intel Achievement Award in 2011 for outstanding innovation in delivering an industry-leading media architecture.
Jiang received his bachelor's degree in electrical engineering from the University of Science and Technology of China. He holds a master's degree in electrical engineering from Academia Sinica, Institute of Electronics, Beijing; and a second master's degree in engineering science from Dartmouth College. He earned his Ph.D. in electrical engineering from the University of Illinois at Urbana-Champaign.
|View Bio Close BioShivnandan D. Kaushik (Shiv)Intel Fellow, Software and Services Group|
Director, Systems Software
Shivnandan (Shiv) Kaushik is an Intel Fellow, Software and Services Group and director of Systems Software. Kaushik directs work on the definition and optimization of platform and firmware interfaces to operating systems and core virtualization software.
Kaushik joined Intel in 1995 as a senior software engineer and has served in a number of software engineering and management roles. He is an expert in the design of platform hardware and firmware interfaces to operating systems and virtualization software. In this role, he has made optimizations for features introduced on Intel processors since the Pentium Pro and contributions to industry standard firmware specifications. Kaushik holds 16 patents with 28 patents pending in the areas of system software and platform architecture. He has received three Intel Achievement Awards.
Kaushik received a bachelor's degree in computer science and engineering from the Indian Institute of Technology, Bombay in 1990. He earned his master's degree and doctorate in computer and information science from The Ohio State University in 1991 and 1995, respectively.
|View Bio Close BioDavid J. KuckIntel Fellow, Software and Services Group |
Director, Hardware and Software Codesign Tools
David J. Kuck is an Intel Fellow in the Software and Solutions Group (SSG) and director of Hardware and Software Codesign Tools for Intel Corporation. He is currently working on the HW/SW codesign of architectures and applications based on performance, energy and cost. Under Kuck's leadership, SSG produced industry leading parallel tools including ThreadChecker, ThreadProfiler, and OpenMP.
Kuck founded KAI in 1979, which produced the KAP vectorization and parallelization tools. KAI was acquired by Intel in 2000. He is an emeritus faculty member of the Computer Science and Electrical and Computer Engineering departments of the University of Illinois at Urbana-Champaign, and was director of the Center for Supercomputing Research and Development.
Kuck holds a bachelor's degree in electrical engineering from the University of Michigan, and Ph.D. from Northwestern University. He is a fellow of the AAAS, ACM, and IEEE, and member of the NAE. He has won a number of awards, most recently the 2010 ACM-IEEE Kennedy Award, and the IEEE Computer Society's 2011 Computer Pioneer Award.
|View Bio Close BioKelin J. KuhnIntel Fellow, Technology and Manufacturing Group|
Director, Advanced Device Technology
Kelin J. Kuhn is an Intel Fellow for the Technology and Manufacturing Group and director of Advanced Device Technology at Intel Corporation. Kuhn is responsible for device architecture path finding for Intel's advanced process technologies.
Kuhn joined Intel in 1997 working on Intel's 0.35 micron process technology. Since then, Kuhn has been involved in Intel's manufacturing process technology development for the 0.35 micron, 130nm, 90nm, 45nm and 22nm technology nodes.
Previously, Kuhn was a tenured faculty member in the Department of Electrical and Computer Engineering at the University of Washington. Kuhn is an IEEE Fellow, the past recipient of a National Science Foundation Presidential Young Investigator Award for her work on strained layer III-V materials and has won two Intel IAA awards, one for her work on Hi-K metal gate transistors and one for her work on the 22nm device architecture. Kuhn is the author of more than 80 technical papers in electronic and photonics, and has also authored a textbook on laser engineering.
Kuhn earned her bachelor's degree in electrical engineering from the University of Washington in 1980. Kuhn received her master's and doctoral degrees in electrical engineering from Stanford University in 1985.
|View Bio Close BioBelliappa KuttannaIntel Fellow, Platform Engineering Group|
Chief Architect, Intel® Atom™ Processor Family
Belliappa (Belli) Kuttanna is an Intel Fellow and chief architect of the Intel® Atom™ processor family for the Platform Engineering Group at Intel Corporation. He is responsible for leading the architectural definition of Intel Atom processors in the Intel Architecture Group. He is additionally responsible for performance analysis of Intel Atom processors and some Intel Atom processor-based phone and tablet system-on-chips (SOCs).
Kuttanna joined Intel in 1999 as an architect in the Austin Texas Design Center. From 2000 to 2003 he served as the co-lead architect of an Intel Pentium® 4 processor derivative. He was the lead hardware architect for Penwell, the first Intel Architecture based phone SoC. Kuttanna worked at Texas Instruments from 1989 to 1991 as an ASIC designer, at Motorola from 1993 to 1997 as a design engineer on PowerPC processors, and at Sun Microsystems from 1997 to 1999 as a SPARC processor micro-architect.
He has been issued 25 patents and he was the recipient of an Intel Achievement Award in 2008.
Kuttanna earned a bachelor's degree in electronics and communication engineering from Karnataka Regional Engineering College, Suratkal, India, in 1989. He earned his Master's degree in Electrical Engineering from Texas A&M University in 1993.
|View Bio Close BioP. Geoffrey LowneyIntel Fellow, Software and Solutions Group|
Chief Technology Officer, Developer Products Division
P. Geoffrey Lowney is an Intel Fellow and chief technology officer for the Developer Products Division of the Software and Solutions Group at Intel Corporation. He is responsible for using advanced compiler technology to improve the performance and usability of Intel Architecture processor family products.
Lowney joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel.
Prior to joining Intel, he was a Compaq Fellow and Director of Compiler and Architecture Development for the Alpha Microprocessor Group. His responsibilities included developing compiler technology and tuning compilers for Alpha systems, providing architectural direction to the microprocessor design teams and designing Alpha architecture extensions.
Before joining Digital Equipment Corporation in 1991, Lowney was a Consulting Engineer at Hewlett-Packard from 1990 to 1991. From 1984 to 1990, he was Director of Compiler Development at Multiflow Computer.
Lowney received his doctorate and master's degrees in computer science and his bachelor's degree in mathematics from Yale University in 1983, 1978 and 1975, respectively. He holds 11 patents in computer architecture and compiler technology.
|View Bio Close BioJose MaizIntel Fellow, Technology and Manufacturing Group|
Director, Logic Technology
Quality and Reliability
Jose Maiz is an Intel Fellow and director of Logic Technology Quality and Reliability. He joined Intel in 1983, and was promoted to fellow in 2002. He is presently responsible for identification of silicon reliability limiters to scaling, and their resolution for Intel's next generation silicon technologies and logic products.
Maiz first joined Intel's 1Mbit DRAM program transitioning to the 1µm logic technology generation. He has since led silicon reliability teams at various phases of development and ramp readiness. Since the mid 80's, Maiz has been a major force in integrating technology reliability with technology development to ensure that Intel's logic processes are robust for reliability while delivering top performance. He has originated or developed many innovative Quality and Reliability methodologies related to transistors, interconnects, Soft errors, Electrostatic Damage protection and assessment of Reliability Risk. He is presently focused on the 10 & 14nm semiconductor technologies and in methods to achieve low power operation in logic devices.
Maiz holds 9 patents. He has authored or co-authored over 35 publications and conference presentations, a number of them invited. He is a co-recipient of an Intel Achievement award and numerous divisional recognition awards. He is a Fulbright Scholar (1978) and was named IEEE Fellow in 2008.
Maiz received his bachelor's degree in physics from the University of Navarra in San Sebastian in 1976. He then moved to the U.S., earning a master's degree of science and a Ph.D in Electrical Engineering from Ohio State University in 1980 and 1983 respectively.
|View Bio Close BioWesley D. McCulloughIntel Fellow, Platform Engineering Group|
Director, Ingredient Productization and Customer Enabling, Microprocessor Development Group
Wesley D. McCullough is an Intel Fellow for the Platform Engineering Group and director of Ingredient Productization and Customer Enabling for the Microprocessor Development Group at Intel Corporation.
In this role, McCullough oversees the development and productization of Intel® Architecture Core products (mobile, desktop, workstation and server computing segments) from the time they first see silicon through product release qualification and high-volume manufacturing. He leads Intel Corporation's post-silicon teams in identifying and solving product issues, optimizing products, enabling and supporting high-volume manufacturing, and providing expert customer enabling support.
Since joining the company in 1989, McCullough has held technical and leadership positions in microprocessor development including key roles in the Intel® 486 DX2 processor, the Intel® Pentium® Pro processor, and the Intel® Pentium 4 processor family of processors. Most recently, McCullough was a key technologist in the development of Intel's latest "Nehalem" generation of microprocessors, the Intel® Core™ i7, Intel® Core™ i5, and Intel® Xeon® processor 5500 series. For Westmere (the 2-core client version of the Nehalem family), McCullough was the chief technologist responsible for product definition as well as overseeing verification, testing and customer support issues. He holds three patents and has written or contributed to 10 papers or publications.
McCullough received his bachelor's degree in electrical engineering from Brigham Young University, Utah, in 1990.
|View Bio Close BioNeal R. MielkeIntel Fellow, Technology and Manufacturing Group |
Director, Reliability Methods
Neal R. Mielke is an Intel Fellow in the Technology and Manufacturing Group and director of Reliability Methods. He joined Intel in 1979 and worked in quality and reliability for non-volatile memories such as EPROMs, E2PROMs and flash. He later worked in the development of non-volatile memories including Intel's original flash products and on the reliability of Intel's logic technologies. Mielke is currently responsible for the reliability of new nonvolatile memory technologies and solid state drives. He has also contributed to the development of algorithms and firmware for solid state drives.
Mielke has led the development of industry standards for the reliability qualification of nonvolatile memory components and solid state drives, and serves on the Board of Directors for the IEEE Reliability Physics Symposium.
Mielke received a bachelor's degree in physics and an master's degree in electrical engineering from Stanford University in 1979. Born in Palo Alto, Calif., he has 22 patents, 23 publications and five Intel Achievement Awards.
|View Bio Close BioAnand S. MurthyIntel Fellow, Technology and Manufacturing Group|
Director, Strained Silicon Process Technology
Anand Murthy is an Intel Fellow and director of Strained Silicon Process Technology at Intel's Portland Technology Development Group in Oregon. He is responsible for leading the pathfinding process development team for advanced strained transistors based on novel epitaxial deposition for 14nm CMOS logic technology node.
Murthy joined Intel in 1995 and was responsible for developing embedded SiGe epitaxial deposition process for industry-leading first-ever strained PMOS transistors at the 90nm technology node. Murthy subsequently led the pathfinding process development for strain enhancement in subsequent technology nodes. He also led the process development and implementation of a novel raised S/D EPI film for NMOS transistors at 32nm node, a first at Intel and in the industry.
Murthy is the recipient of four Intel Achievement Awards and the 2008 SEMI North American Award for "Process Integration of Strain-enhanced Mobility Techniques for CMOS Transistors." He has co-authored papers in more than 40 technical publications and holds 58 patents, the majority of them granted for his work in epitaxial deposition to enable strained transistors.
Murthy earned a bachelor's degree from the Indian Institute of Technology, Banaras Hindu University, in 1987. He earned a master's degree from The Ohio State University in 1988, and a Ph.D. in materials science and engineering from University of Southern California in 1993.
|View Bio Close BioPaul A. PackanIntel Fellow, Technology and Manufacturing Group|
Director, Transistor Technology Development
Paul Packan is an Intel Fellow, Technology and Manufacturing Group, and director of Transistor Technology Development. In this role, he currently leads Intel Corporation's 15nm device technology group. Among his recent successes is delivering Intel's 32nm device technology to production including Intel's second-generation high-k and fourth-generation strained silicon technologies.
Packan joined Intel in 1992, leading the process and device simulation group in applying TCAD simulations to develop and optimize Intel's 0.35µm, 0.25µm and 0.18µm process technologies focusing on device and process architecture. In 1998, he began leading the process and device modeling group, developing advanced models for ion implantation, dopant diffusion, carrier transport, carrier mobility and quantum effects to enable exploration of novel process and device technologies. In 2001, he assumed ownership of the compact device modeling group, delivering the industry's first surface potential-based compact device model for circuit level simulation to enable accurate digital, analog, RF and noise modeling.
He has been issued more than 10 patents in the area of transistor architecture and has authored or co-authored more than 30 papers.
Packan received his bachelor's degree in electrical engineering from the University of Washington in 1984, and his master's and doctorate in electrical engineering from Stanford University in 1985 and 1991, respectively.
|View Bio Close BioMario J. PanicciaIntel Fellow, Data Center Group|
General Manager, Silicon Photonics Solutions Group
Mario J. Paniccia is an Intel Fellow and general manager of the Silicon Photonics Solutions Group for the Data Center Group and Intel Corporation.
Paniccia joined Intel in 1995 as a lead researcher developing a novel optical testing technology for probing transistor timing in microprocessors. Today this optical testing technology is the standard in the industry. During his tenure at Intel he has served in various roles from research and development to strategic direction setting to driving the development and commercialization of technologies needed to enable optical communications and/or optical interconnects in and around Intel platforms. Paniccia started Intel's research in the area of Silicon Photonics and currently leads the business unit driving silicon photonics product commercialization, which includes engineering, business, and strategy as well as defining future generation products.
Paniccia's team has pioneered activities in silicon photonics that have led to the world's first silicon modulator with a bandwidth greater than 1GHz (2004) and then in 2007, performance was pushed to 40Gb/s. In addition his team has demonstrated the world's first continuous wave silicon laser (2005), and together with University of Santa Barbara they demonstrated the world's first "Hybrid Silicon Laser" (2006). In 2007 his team demonstrated the world's best performing SiGe waveguide based Photo-detector operating at 40Gb/s.
Scientific American named Paniccia one of 2004's top 50 researchers for his team's leading work in the area of silicon photonics. In October 2008 Paniccia was named by R&D Magazine as "Scientist of the Year" for his teams pioneering research in the area of Silicon Photonics. In 2011 Paniccia was named "Innovator of the year" by EE times for his teams demonstration of the world's first integrated 50Gbps Silicon photonics link.
Paniccia has received two Intel Achievement Awards and has published numerous papers, including three Nature papers, three Nature Photonics papers, three book chapters, and has over 67 patents issued or pending. He is a fellow of the IEEE, SPIE and OSA.
Paniccia earned a bachelor's degree in physics in 1988 from the State University of New York at Binghamton and a Ph.D. in solid state physics from Purdue University in 1994. In May 2009 Paniccia was awarded an Honorary Doctorate Degree from Binghamton University.
For more information on silicon photonics, visit www.intel.com/go/sp.
|View Bio Close BioDavid B. PapworthIntel Fellow, Legal and Corporate Affairs|
Director, Microprocessor Product Development
David B. Papworth is an Intel Fellow, Legal and Corporate Affairs and the director of Microprocessor Product Development for Intel Corporation. Papworth designs next-generation microprocessor architectures, including concept development, performance analysis, resolution of detailed design and compatibility issues, and interaction with software developers. He also provides technical direction and expertise in moving new designs and proliferations from silicon to production and launch.
Papworth joined Intel in 1990 as a staff VLSI architect. He was one of the lead architects of the Pentium® Pro microprocessor. In 1994, he became principal processor architect, responsible for the system debugging of the Pentium Pro processor. His team received an Intel Achievement Award and an Intel Quality Award in 1996 for the Pentium Pro microarchitecture. He also receive an Intel Achievement Award in 1997, for the design and use of the P6 Microcode Update facility. Papworth is named as inventor or co-inventor on 56 patents for microprocessors, computers, and computer systems.
Papworth was born in Hancock, Mich., in 1956. He received his bachelor's degree in Electrical Engineering from the University of Michigan, Ann Arbor, in 1979. Prior to Intel, Papworth worked at Multiflow Computer as director of hardware engineering, and at Prime Computer as a principal engineer designing digital logic for super-minicomputers.
|View Bio Close BioKrishna ParatIntel Fellow, Technology and Manufacturing Group|
Director, NAND Cell Research and Development
Krishna Parat is an Intel Fellow and the director of NAND cell research and development in the Intel Non-Volatile Memory Solutions Group. He oversees the NAND Flash Device Group and is currently responsible for developing Intel's NAND Flash scaling roadmap beyond the 20-nanometer (20nm) node.
Parat has played a key role in developing Intel's Flash memory technologies. He co-led the team responsible for the research and development of Intel's industry-leading 20nm NAND Flash technology. From 2006 to 2008 he co-led the cell development for Intel's 50nm and 34nm NAND Flash technology. From 1996 to 2005, he co-led the development of several generations of Intel's NOR Flash technology, beginning with 0.25 micron through 90nm. Parat joined Intel in 1991 as a device engineer working on 0.60micron NOR Flash technology.
A recognized expert in non-volatile memory technology, Parat is frequently invited to speak and present papers at industry-sponsored workshops and symposiums. He has written or co-authored more than 30 presentations and papers since 1987. Parat has also been honored with three Intel Achievement Awards - two for his work on NOR Flash and one for establishing Intel's NAND cell scaling leadership with 34nm technology.
Parat holds 16 U.S. patents and has filed more than a dozen additional patent applications that are currently pending. An active member of the Institute of Electrical and Electronics Engineers (IEEE), Parat in 1985 earned his B. Tech. degree in electrical engineering from the Indian Institute of Technology in Chennai, India. He also holds a master's degree in electrical engineering and a Ph.D. in electrical engineering, both from Rensselaer Polytechnic Institute.
|View Bio Close BioRadia PerlmanIntel Fellow, Intel Labs|
Director, Network and Security Technology
Radia Perlman is an Intel Fellow and director of Network and Security Technology in Intel Labs.
Perlman joined Intel in 2010 and focuses on Intel Labs' leadership in network and security. She provides strategic direction for future network, security and trusted platform research. Prior to joining Intel, Perlman was with Sun Microsystems, where she was a Sun Fellow.
Perlman is the inventor of many fundamental technology innovations in computer networking, including the spanning tree algorithm, which is at the heart of today's Ethernet; TRILL, an emerging standard for data center interconnection that can replace today's spanning tree Ethernet; and scalable and robust link state routing technology that is key to the operation of today's Internet. Her design for DECnet routing became standardized by ISO as the IS-IS protocol, which is deployed in many ISPs, and is the basis of the IETF's TRILL standard.
Perlman is also responsible for many innovations in security, including assured delete of data, distributed algorithms robust despite malicious trusted components, and usable trust models for PKI. Perlman has authored two networking textbooks, widely used in both universities and industry; written 20 technical papers; and holds about 100 patents.
Perlman has been recognized with numerous industry awards including an honorary doctorate from KTH Royal Institute of Technology in Sweden, the Usenix Association lifetime achievement award, Silicon Valley Inventor of the year in 2004 and the Women of Vision Award for Innovation in 2005.
Perlman received her bachelor's and master's degrees in mathematics, and a Ph.D. in computer science from the Massachusetts Institute of Technology (MIT).
|View Bio Close BioDevadas D. PillaiIntel Fellow, Technology and Manufacturing Group|
Director, Operational Decision Support Technology
Intel Fellow Devadas (Dev) Pillai is the Director of Operational Decision Support Technology in the Logic Technology Development group, based in Chandler, Arizona. He is currently responsible for development and proliferation of manufacturing simulation technology and mathematical modeling & optimization capabilities across Intel's wafer fabrication, sort, assembly and test factories worldwide.
Pillai is Intel's first fellow whose technical expertise spans production simulation, robotics and factory automation. He has been honored many times by his industry peers as one of the most influential engineers who drove the vision and industry direction for large scale factory automation in semiconductor manufacturing.
Pillai introduced the use of computer simulation technology for Intel's factory operational designs beginning in 1986. From 1989 to 1994, he was the Design Engineering Manager of the Automated Material Handling Systems Group and led the company's successful 150mm and 200mm robotic transport systems development. From 1994 to 2000, he was Factory Integration Manager who coordinated Intel's highly successful 300mm production equipment, facilities and automation interface standardization and interoperability development with the worldwide consortia. Prior to his current position, he managed Intel's Enabling Technologies and Solutions group that was responsible for yield, fault isolation and failure analysis tools, process and production control systems, knowledge management capabilities and machine learning programs. Prior to Intel, Pillai was a development engineer at Ford Trucks.
Pillai is the recipient of two Intel Achievement Awards. In 2000, he was recognized by the National Academy of Engineering at the Frontiers of Engineering conference. He has written more than 90 peer-reviewed technical papers and presentations in IEEE, ISSM, SME, JES, IIE and SEMI publication in the fields of factory automation, 300mm factory design, and simulation modeling. He has also written a section on automation in the McGraw Hill Encyclopedia of Science and Technology and has co-authored a chapter in the Handbook of Semiconductor Manufacturing Technology, published by Marcel Dekker.
Pillai received his master's degree in Industrial Engineering specializing in computer-aided processes, from Arizona State University in December 1983 and his bachelor's degree in Mechanical Engineering from the National Institute of Technology, Calicut, India, in 1980.
|View Bio Close BioValluri RaoIntel Fellow, Technology and Manufacturing Group |
Director, Analytical and Microsystems Technologies
Dr. Valluri Rao is an Intel Fellow and director of Analytical and Microsystems Technology in Intel's Technology and Manufacturing Group. He is responsible for research into heterogeneous integration of different technologies for Intel's CMOS Silicon and SOC platforms. Rao is also an IEEE Fellow.
Rao joined Intel in 1983 and pioneered numerous silicon characterization techniques for microprocessor performance, debug and yield enhancement. Some of these techniques included electron beam based and Ultra-fast optical measurement from microprocessors and silicon micromachining methods for on chip reconfiguring and repairing of circuits for product validation. Rao, who was named an Intel Fellow in 2000, worked on Intel microprocessors starting from the 80386 to the first generation of Itanium processors. Beginning in 2001, Rao initiated Intel's MEMS work by establishing a research and development team to develop reconfigurable RF front end systems for multi radio coexistence. To enable this, advanced RF MEMS switches and novel silicon integration schemes were developed.
He also initiated Intel's early work on optical interconnects and led Intel's first Opto-Electronics research committee for overseeing university-based optical research.
Rao holds more than 80 issued patents. He has earned three Intel Achievement Awards for his work on microprocessor characterization and has published more than 20 external and 10 internal papers.
Rao graduated in 1975 with a first class honors in the Electrical Sciences Tripos from Jesus College, Cambridge University, from where he also received master's (1978) and Ph.D. (1979) degrees in electrical engineering. He was a post-doctoral research fellow at the Cambridge University Engineering Department from 1979 to 1983.
|View Bio Close BioRobert L. SankmanIntel Fellow, Technology and Manufacturing Group|
Director, Package Pathfinding, Assembly Test Technology Development
Bob Sankman is an Intel Fellow and director of package pathfinding in the Assembly Test Technology Development group at Intel Corporation. He is responsible for directing the definition of packaging and assembly activities for Intel's advanced logic products.
Before assuming his current role, Sankman served as the pathfinding and planning manager for the Assembly Test Technology Development group, where he was responsible for defining packaging technology to support all Intel logic processes. Earlier in his Intel career, Sankman was the group's design and core competency manager, a position in which he designed product packages and provided modeling support for assembly technology development. Sankman joined Intel in 1980 as a process engineer during the startup of Intel's Fab 6 facility in Chandler, Ariz.
Sankman holds 29 patents in the field of electronic packaging and has been honored with three Intel Achievement Awards - two in the area of semiconductor fabrication and one in semiconductor packaging. He has also contributed his expertise to numerous papers.
Sankman earned his bachelor's degree in chemical engineering from the University of Illinois in 1980.
|View Bio Close BioVivek K. SinghIntel Fellow, Technology and Manufacturing Group|
Director, Computational Lithography
Vivek Singh is an Intel Fellow and director of computational lithography in Intel's Technology and Manufacturing Group.
He is responsible for all of Intel's CAD and modeling tool development in full chip OPC, lithography verification, rigorous lithography modeling, next-generation lithography selection, inverse lithography technologies and double patterning. He also represents Intel on several external Design for Manufacturability (DFM) forums, and is currently chairman of the SPIE DFM Conference.
Singh joined Intel in 1993 as a modeling applications engineer, was appointed team leader for the Resist and Applications Group in 1996, and was appointed overall leader of the Lithography Modeling Group in 2000.
He holds 13 patents, has published 38 technical papers and won the Intel Achievement Award in 2007.
Singh graduated from the Indian Institute of Technology in Delhi with a bachelor's degree in chemical engineering in 1989. He earned a master's degree in chemical engineering in 1990, a Ph.D. minor in electrical engineering in 1993, and a Ph.D. in chemical engineering in 1993, all from Stanford University.
|View Bio Close BioSwaminathan SivakumarIntel Fellow, Technology and Manufacturing Group |
Swaminathan "Sam" Sivakumar is an Intel Fellow and director of Lithography in Intel's Portland Technology Development Group in Oregon. He is responsible for the definition, development and deployment of Intel's next generation lithography processes, resolution enhancement techniques and optical proximity correction.
Sivakumar joined Intel in 1990 and throughout his career with the company has worked in the lithography area on photoresists, patterning equipment and process development. He has contributed to lithography development, characterization and transfer to high-volume manufacturing of every submicron process technology generation at Intel since 1990. He co-invented industry-leading interconnect patterning techniques for aluminum metallization on the 180 nanometer process as well as for dual-damascene copper metallization on the 130 nanometer and newer processes.
Sivakumar received his bachelor's degree in electrical engineering from the Indian Institute of Technology in Madras, India in 1987. He received his master's degree, also in electrical engineering from the University of Illinois at Urbana-Champaign in 1989.
Sivakumar has received three Intel Achievement Awards for his work on P854 speed performance and for development of advanced aluminum and dual-damascene copper interconnect processes. He has published 14 papers on semiconductor processing. He holds 30 patents on lithography and patterning.
Sivakumar was born in 1966 in Madras, India.
|View Bio Close BioJoseph M. SteigerwaldIntel Fellow, Technology and Manufacturing Group|
Director, Chemical Mechanical Polish Technology
Joe Steigerwald is an Intel Fellow and director of Chemical Mechanical Polish Technology, Intel Technology and Manufacturing Group. He is responsible for pathfinding, development, and transfer to high volume manufacturing of advanced chemical metal polish (CMP) and metals deposition modules for Intel's 32nm, 22nm, and 16nm logic and advanced memory technologies.
Steigerwald originally joined Intel in 1988 as a fab etch engineer. He left for a brief time to pursue advanced electrical engineering degrees and has been with the company continuously since 1995. He has held a number of leadership roles in the company's Portland Technology Development organization, primarily in the CMP area. His work in CMP has lead to major advancements in this critical technology, enabling key elements of Intel's silicon process architecture.
Steigerwald has written one book and one book chapter and hold three patents for advances in his CMP area of expertise. His work has appeared in more than a dozen journal publications and he has made numerous technical conference and workshop presentations.
Originally from Upstate New York, Steigerwald received his bachelor's degree in electrical engineering from Clarkson University in 1988. He received his masters and doctorate degrees in electrical engineering from Rensselaer Polytechnic Institute in 1993 and 1995, respectively.
|View Bio Close BioMichael J. StetterIntel Fellow, Platform Engineering Group|
Chief Platform Technology Officer
Michael Stetter is an Intel Fellow and chief platform technology officer for the Platform Engineering Group at Intel Corporation. Stetter develops products and solutions for mobile communications, including smartphones, tablets and entry-level mobile phones. Stetter is responsible for external silicon foundry technology strategy and technology platform target-setting, as well as for leading a strategic initiative to enable product cost leadership for entry/value smartphone and next-generation LTE slim modem products on in-house technologies.
Stetter joined Intel in 2011 when the company completed its acquisition of Infineon Technologies' wireless solutions business. Earlier in his career, he spent 13 years at Siemens HL/Infineon in various technology research and development positions. During his tenure there, he proposed and implemented the multi-sourcing strategy that enabled simultaneous sourcing from Charted and Taiwan Semiconductor Manufacturing Company for 65-nanometer technology generations. Later, United Microelectronics Corp. was added as well.
From 1998 to 2001, Stetter was part of a manufacturing development alliance between IBM, Infineon and Samsung in East Fishkill, N.Y., where his responsibilities included leading the back-end and front-end multinational integration teams. While Stetter was in that role, the management team representing the three alliance partners recognized him as "Inventor of the Year." Other positions in his career included leading a research team at GSI Darmstadt (Gesellschaft für Schwerionenforschung) and a 3-year, internationally funded research project at CERN (the European Organization for Nuclear Research).
Stetter holds 11 patents in the field of plasma physics and CMOS process integration, and has authored roughly 18 papers and publications on the same topic. He received his master's degree in physics from the University of Erlangen in Nürnberg, Germany, and his Ph.D. in physics from Friedrich-Alexander University Erlangen, also in Nürnberg.
|View Bio Close BioKenneth StewartIntel Fellow, Platform Engineering Group|
Chief Wireless Technologist
Dr. Kenneth (Ken) Stewart is an Intel Fellow and chief wireless technologist for the Platform Engineering Group at Intel Corporation. Over the past 25 years in the industry, Stewart has contributed strongly to fundamental research in mobile wireless technologies including GSM, CDMA, WCDMA and LTE, and to the development of the associated 3GPP international wireless standards, particularly HSPA, LTE and LTE-Advanced. He has engineered and reduced to practice base station and mobile solutions based on the same technologies.
Most recently, Stewart was CTO for TE Connectivity's wireless division, where he drove innovation and product development for advanced small cell and distributed antenna systems, wavelength division multiplexed fiber distributed radio access networks, coordinated multipoint transmission systems and solutions for broadband wireless access infrastructure.
Previously, Stewart was vice president of Standards and Research at Motorola Mobile Devices, where he was responsible for international standards and research work in areas ranging from radio access networks, through multimedia systems to mobile applications and services. He served as advisor to Motorola Mobile Devices senior leadership on fundamental technical and strategic issues regarding the performance and evolution of radio access networks and multimedia technology.
Stewart has held the position of Motorola Dan Noble Fellow and served on Motorola's Science Advisory Board. He holds more than 35 issued patents, with multiple patents pending. He is a graduate of the Institute for Communications and Signal Processing at the University of Strathclyde, where he is also Visiting Professor.
|View Bio Close BioGregory F. TaylorIntel Fellow, Platform Engineering Group|
Chief Architect, Hard IP Group
Greg Taylor is an Intel Fellow and Chief Architect in IPG's Hard IP group. His interests include Systems on a Chip, Analog/Mixed Signal circuits, and Wireless.
Taylor joined Intel in 1991 and has held several senior design engineering positions working on 10 generations of microprocessors including members of Intel's Pentium®, Pentium® II, Pentium® III, and Intel NetBurst® microarchitecture families. Prior to joining Intel, he worked as a principal engineer at Bipolar Integrated Technology.
Taylor has received an Intel Achievement Award for his work on deploying advanced packaging. He has published over 60 papers and holds over 60 patents on integrated circuit design and test. Taylor is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE).
Taylor received his doctorate in computer and systems engineering in 1985 from Rensselaer Polytechnic Institute. His graduate work was completed with the support of a Fellowship from the Fannie and John Hertz Foundation.
|View Bio Close BioKeshavan K TiruvallurIntel Fellow, Platform Engineering Group|
Platform Validation Engineering
Keshavan K Tiruvallur is an Intel Fellow in Platform Validation Engineering for the Platform Engineering Group at Intel Corporation. He is responsible for the technical oversight on the post-silicon validation debug process and methods. He is currently leading enhanced platform debug capabilities within Intel as well for Intel's customers in this new era of increased integration.
Tiruvallur joined Intel in 1983 immediately after graduating from college. His first job was computer board test engineer. He has subsequently worked as a BIOS engineer, in firmware, board design, board design evaluation and board test.
He has also worked on microprocessor architecture, taking on such roles as a microcoder, microarchitect and DFx architect. He has developed extensive microcode for the Intel architecture family of products starting with Intel Pentium® Pro, Intel Pentium® II/III family and Intel Pentium® 4 family. Tiruvallur led the microcode team through the Nehalem/Westmere processor family development. He was the lead DFx architect and system debug lead on Nehalem/Westmere family of processors. He has been the IA legacy microarchitect, responsible for maintaining IA legacy features across generations.
He has 14 patents issued or pending, and has won three Intel Achievement Awards.
Tiruvallur earned his bachelor's degree in electrical engineering from B.M. Sreenivasaiah (BMS) College of Engineering, Bangalore, India, in 1978. He earned his master's degree in computer engineering from the University of Memphis in 1983.
|View Bio Close BioBrendan TrawIntel Fellow, Platform Engineering Group|
Director, Capability Access
Brendan Traw is an Intel Fellow and director of Capability Access for the Platform Engineering Group at Intel Corporation. In this role he is responsible for establishing a consistent set of capabilities across devices to enable new user experiences.
Previously, Traw was the CTO for Intel's Digital Home business and has focused on the management and protection of entertainment content in digital environments, leading the team which developed Digital Transmission Content Protection (DTCP), the basis for content protection in today's digital home networks, as well as a range of other content protection solutions for recordable DVD, DVD-Audio, SDcard, and the DVI/HDMI display interfaces.
A recognized leader across the computer, consumer electronics and content industries, Traw has published numerous papers and holds 30 patents in the areas of content protection, system architecture and network security. He is a two-time recipient of the Intel Achievement Award.
Traw earned a Ph.D. in computer information science from the University of Pennsylvania prior to joining Intel in 1995.
|View Bio Close BioRichard A. UhligIntel Fellow, Intel Labs|
Director, Systems and Software Research
Rich Uhlig is an Intel Fellow and director of Systems and Software Research in Intel Labs, where he leads research efforts in virtualization, software-defined networking, cloud storage, persistent memories, big-data analytics, and programming systems. Uhlig is also the executive sponsor for the Intel Science and Technology Centers (ISTCs) for Cloud Computing (centered at CMU) and Big Data (centered at MIT).
In past work, Uhlig started virtualization efforts within Intel in 1998 and led the definition of multiple generations of virtualization architecture for Intel processors and platforms, known collectively as "Intel Virtualization Technology" (Intel® VT). Intel VT is used today in a variety of settings and applications to improve the utilization, management, availability and security of systems based on Intel architecture.
Prior to joining Intel in 1996, Uhlig held post-doctoral fellowships at the European national research labs of Germany, Greece, and France, where he worked on advancing simulation technology and on architectural support for microkernel operating-system design.
Uhlig has published over 20 technical papers, holds 24 patents, and has received two Intel Achievement Awards for his work on system simulation and Intel® VT. He earned the Ph.D. in Computer Science and Engineering from the University of Michigan in 1995.
|View Bio Close BioOfri WechslerIntel Fellow, Platform Engineering Group|
Director, Visual and Parallel Architecture Group
Ofri Wechsler is an Intel Fellow and director of Visual and Parallel Architecture Group (VPG) for the Platform Engineering Group at Intel Corporation. In this role Wechsler is responsible for the architecture development of the Many Integrated Cores (MIC) product line including Knights Corner, Knights Landing and Knights Hill. In addition Wechsler is also responsible for the Processor GFX (PG) media architecture from the Skylake generation and beyond. In the last two years Wechsler also led the "IA GFX Proof-of-concept" attempting to to implement a software rendering 3D pipeline on a MIC architecture.
Prior to heading VPG Architecture Wechsler spent 10 years leading the CPU architecture team in in Israel. In this role Wechsler was responsible for the architecture development of many CPU generations including Skylake, Sandy Bridge, Ivy Bridge, Merom, Penryn, Banias, Dothan and Yonah. Previously, Wechsler served as platform architect for the Timna platform. He also served as manager for the Israel Design Center Architecture Validation team, responsible for the validation of the P55C version of the Intel® Pentium® processor. Wechsler joined Intel in 1988 as a design engineer for the i860.
Wechsler received his bachelor's degree in electrical engineering from Ben Gurion University, Beer Sheva, Israel, in 1989. He has four U.S. patents.
|View Bio Close BioKevin X. ZhangVice President, Technology and Manufacturing Group|
Director, Advanced Design, Logic Technology Development
Kevin Zhang is an Intel Fellow and vice president in the Technology and Manufacturing Group at Intel Corporation and director of advanced design in logic technology development. He is responsible for advanced circuit technology development for the company's future products. Zhang oversees the development of process design rules, digital circuit libraries, key analog and mixed-signal circuits, high-speed I/Os and embedded memories. He is also responsible for delivering the first technology vehicles for each new logic technology development at Intel.
Since joining Intel in 1997, Zhang has held several technical and management positions. Prior to his current role, he led Intel's embedded memory technology development from 90-nanometer (90nm) to 22nm generations. In 2005, Zhang was appointed an Intel Fellow for his technical leadership in memory technology. He has led his teams to win five Intel Achievement Awards in the area of advanced memory and digital circuit technology development.
Zhang has published more than 55 papers at international conferences and in technical journals and is the editor of Embedded Memory for Nano-Scale VLSIs, published by Springer in 2009. He holds more than 45 U.S. patents in the field of integrated circuit technology. Zhang chairs the memory subcommittee of the International Solid-State Circuits Conference (ISSCC) and is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE).
Zhang received his bachelor's degree from Tsinghua University in Beijing in 1987 and his Ph.D. from Duke University in 1994, both in electrical engineering.