Intel® Telecom Products Packet Switched Backplane Solutions

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Intel® Telecom Products

Ethernet Everywhere

Intel's Packet Switched Backplane Solutions

Intel offers a comprehensive set of carrier-grade, standards-based CompactPCI* building block solutions for telecommunications and the Internet. With introduction of the PICMG* 2.16 (Packet Switching Backplane), 2.9 (System Management) and 2.7 (Dual System Slot) specifications, Intel is delivering Ethernet everywhere, enabling next-generation connectivity and processing in the network.

The PICMG 2.16 specification reduces costs and simplifies development by building on existing standards such as CompactPCI, Ethernet and transmission control protocol/Internet protocol (TCP/IP). By blending the high-availability and hot swap capabilities of CompactPCI with the broad acceptance of Ethernet, this specification provides customers a scalable path to the next-generation Internet and voice communications network.


	Learn about High Availability

	Compute Boards and Platform Products

	*Grass Valley Group Aqua Internet Encoder Case Study**

	Moving to IP-based Telco Applications White Paper

	*Q and A for Intel's CompactPCI Building Block Components**

What is PICMG 2.16
The CompactPCI packet switched backplane (PSB) specification describes a redundant, switched 10/100/1000 Ethernet network within a CompactPCI chassis, providing IP connectivity between all CompactPCI and/or CompactPCI/PSB slots using a "star" topology. It is intended to coexist with a 64-bit CompactPCI bus and H.110 bus, and therefore allocates the pins for CompactPCI/PSB links on J3 of all peripheral slots. Special slots for active switching fabric elements, which may be redundant, are also specified.

The CompactPCI/PSB can support full 21-slot backplanes, multiple enclosures (forming large "virtual" backplanes), full backplane redundancy down to the slot level, scalable bit rate (10/100/1000/2000 Megabit) per slot, selectable chassis bandwidths of between 200 Megabit and 40 Gigabit, link layer flow control, QoS/CoS support, a concise pin-out (20 pins) per slot, and many other advanced features.

Benefits of Packet Switched Backplane Technology

Architectural Scalability
Backplane interconnect speeds are user-definable, scalable from 10 Mbps to 2000 Mbps (dual-star Ethernet full duplex) per node slot. This allows customers to start with a lower-cost, lower-speed set of components, and upgrade performance by swapping nodes or fabric components, as needed.
Improved Density
With the switch included in the chassis, no extra rack height is lost. Customers can flexibly connect one to 21 node slots in the same chassis.
Increased System Reliability
All slots are served by redundant fabric connections, allowing for full system failover in the event of a fabric failure. Both switches use the same highly reliable power and cooling in the chassis. As part of Intel's fully IPMI-managed (Intelligent Platform Management Interface) architecture, power and cooling systems may be remotely monitored and can be proactively serviced, thus avoiding possible system failure.
IP/Ethernet Ecosystem
IP/Ethernet is synonymous with the Internet. Use of PICMG 2.16-enabled products can accelerate convergence of telecom and IP-based Internet applications.
Accelerated System Development
By using standards-based modules rather than custom components, customers can focus on their core competence of building the next-generation application set.

Packet Switched Backplane Applications
The packet switched backplane specification is ideally suited to support applications running comfortably over 200 Mbps Ethernet today, such as those built around the TCP/IP protocol stack, and scaling to 2 Gbytes Ethernet in the near future. Web servers, email servers, cache servers, VPN switches and media gateways can all benefit from the packet switched backplane platform. Others applications include:

2.5G wireless
3G wireless
Server clusters
IP DSLAM
VoIP media gateway
Voice/Video/Data servers