Page 12, lines 7 and 8 below Figure 1.5:
There is a missing sentence. It should read: "PCI/PCI Bridges C, between PCI bus segments (3) and (2), and B, between PCI bus segments (2) and (0), must each arbitrate for bus ownership of their respective bus segments and forward the bus transaction to main memory."

Page 12, Figure 1.5 PCI PCI Platform with Hierarchical Bus:
The diagram is missing a bridge between PCI bus segment (0) and PCI bus segment (1).

Page 429, Figure 9.1:
"PCIEX" should be deleted.

Page 435, Figure 9.3:
"PCIEX" should be "PCIEXP".

Page 437, Figure 9.4:
The figure references C, D, and E that refer to "Fig. 9-2" should be changed as follows: C and E refer to Fig. 9.2 and D refers to Figs. 9.1 and 9.2.

Page 597, Figure 12.5 -- Initialize and enable all counters box:
"Nak_Sch flag=0B" should be "Nak_Sch flag=0b".

Page 755, Section titled "Transition L1 Link State to L0 Link State":
The phrase "An endpoint, switch, or bridge as the USD..." should read "An endpoint, switch, or bridge as the DSD..."

Page 770, Figure 15.4:e heading "Non-Mobile Add-in Cards" Insert the following paragraph:The phrase "The USD can independently transition its DS port from L1 to L0s..." in the box on the right hand side should be "USD can independently transition its DS port from L0 to L0s..."

Page 787, Figure 16.2:
On the downstream port of the right hand of the Root Complex box, the following text should be added above the shaded box of the port: "Root Complex Cont. & Status Reg."

Page 788, Bulleted list item "Root Status Register":
Replace the text "Root Status Register: See following discussion" with the following:

"Root Status Register: This register provides the Requester ID (BUS#, DEVICE#, and FUNCTION#) of the PCI Express device that sources the message PM_PME requester transaction packet related to a wakeup event. It also indicates if any of these transactions are pending."

Page 803, "Slot Power Limit Protocol Implementation" - 2nd sentence:
"Slow Power Limit Scale" should be "Slot Power Limit Scale."

Page 805, 1st paragraph:
The phrase, "when link transitions" should read "when its DLCMSM transitions."

Page 817, sentence after run-in heading "First Assert of A and B":
Sentence should read as follows: "When the upstream port determines that interrupt A has been asserted, it transmits upstream a message Assert_INTA requester transaction packet per the following considerations."

Page 836, "Other EHA Considerations" 2nd paragraph:
The term "unlock message" should be "message unlock."

Page 842, immediately before heading "Non-Mobile Add-in Cards" Insert the following paragraph:
The non-mobile add-in cards define a collection of card sizes based directly on the short length, standard length, and low profile add-in card standards established by PCI. The typical application for the non-mobile add-in cards are desktop PCs and servers. The mobile add-in cards are defined by a single specific add-in card called Mini PCI Express Card indirectly based on the Mini PCI Card Type III. At the print time of this book, several specialty add-in cards have also been announced. NEWCARD is defined by the PCMICA group as the replacement for Cardbus. Server I/O Modules in four self-contained modules form factors. Advance TCAs is defined as carrier grade communications equipment. And finally, Cable Modules defined for enterprise class systems. This book focuses on non-mobile and mobile add-in cards as defined by the PCI Express Base Specification revision 1.0a April 15, 2003, PCI Express Card Electromechanical Specification revision 1.0a April 15, 2003, and Mini PCI Express Card Electromechanical Specification revision 1.0 March 19, 2003.

Page 845, Table 21.2, third row, Side B:
For pin #3, replace "Reserved" with "+12 V" as Signal Line Name.

Page 852, Table 12.7, rows 4 and 12:
For pin #7, replace "Reserved" with "CLKREQ#" as Signal Line Name. For pin #24, replace "3.3 v" with 3.3 Vaux" as Signal Line Name.

Page 856, Bulleted list, immediatly after third item:
Insert this text as new fourth item: "CLKREQ# (Output from item add-in card … mobile add-in cards only): For mobile add-in cards that implement the PCI Express the assertion (active low) of this signal lines enables the REFCLK to be sourced from the platform to the add-in card. This is an open collector signal line."

Page 860, First paragraph on page:
Replace the sentence "Once the 8/10b encoding has occurred, the resulting symbol stream representing the Physical Packet is parsed across the configured lanes of each configured link."
with this sentence "The symbol stream representing the Physical Packet is parsed across the configured lanes of each configured link and then 8/10b encoding is applied."

Page 860, "Receiving Port" section (bottom paragraph):
Replace the sentence "The resulting (bottom paragraph) symbol…stream of 8-bit bytes."
with the sentence "On each lane, the symbol stream of 10 bits is decoded into a stream of 8-bit bytes. The resulting byte streams from the two lanes are de-parsed into a single byte stream."

Page 861, text below Figure 21.2 (bottom), first sentence of paragraph:
Last part of sentence should read "...and to identify DLLPs and LLTPs via the FRAMING symbols."

Page 863, third and fourth lines at top of page:
The sentence beginning "At the receiving port..." should read "At the receiving port, the descrambling is applied right after the 10/8b decoding, as shown in Figure 21.3."

Page 867, fourth paragraph:
The word "hierarchy" should be replaced with "fabric" to be more consistent with commonly accepted PCIE express terminology.

Page 967,box heading, middle of page:
The register block labeled "Slot Capabilities Register (Offset 14Ch)" should read "Slot Capabilities Register (Offset 14h).