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Brief Description

System analysis for industry buses, budgeting, cost/performance trade off, system bussing block diagrams, case studies for SCSI, IDE, Serial ATA, GTL, DDR, PCI, PCI express, and the industry’s direction on new buses.

OBJECTIVES

To develop the skills for analyzing high-speed circuits with signal behavior modeling;
To demonstrate proficiency in understanding signal integrity concepts and terminology and to understand the signal integrity on circuit design;
To be able to perform and analyze signal measurements and to be able make trade off decisions based on signal budget and design requirements.

Syllabus

Signal Integrity on System Bus Technology Course Objectives

 

Course Materials

 

Lectures 1-2

Behavioral Buffer Modeling with Hspice

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Lectures 3-4

Clock Design

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Lecture 5-6

I/O Power Delivery

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Lectures 7-9

Introduction to Frequency Domain Analysis

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Lectures 10-12

Differential Signaling

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8b10b Check XLS Sheet

Lectures 13-14

GHz Differential Signaling

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Lectures 15-16

Peak Distortion ISI Analysis

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Lecture 17

Allegro Free Viewer 15 Demo

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Lectures 18-19

Oscilloscope Capabilities Demo

Tektronix Slides
Network Analyzer Slides

Lectures 20-21

Lab: DDR Signaling and Measurement

KC Lab Board Slides
DDR Signaling Slides
DDR Behave Hspice ckt
Lab 1 Instructions


For Video corresponding to these lectures please check at : http://cdcsi.fm.ith.intel.com/sicourse2.aspx?sm=5*
 

Course Syllabus: SIGNAL INTEGRITY ON SYSTEM BUS TECHNOLOGY – ELCT865

Brief Description

System analysis for industry buses, budgeting, cost/performance trade off, system bussing block diagrams, case studies for SCSI, IDE, Serial ATA, GTL, DDR, PCI, PCI express, and the industry’s direction on new buses.

OBJECTIVES

To develop the skills for analyzing high-speed circuits with signal behavior modeling;

To demonstrate proficiency in understanding signal integrity concepts and terminology and to understand the signal integrity on circuit design;

To be able to perform and analyze signal measurements and to be able make trade off decisions based on signal budget and design requirements.

MAJOR TOPICS

System Analysis for Industry Buses
  Open Collector, Differential, Common Clocking, Source Synchronous

Budgeting
  Timing & Voltage Margins, Uncertainty, Measurement and simulation accuracy

Cost/Performance Trade Off
  Likelihood of failures, oxide failures, cost of failure, error correcting

Clocking
  Clock Domains, Routing topologies, Skew, Jitter, Clock measurements

Case Studies (time permitting)
  SCSI, differential SCSI, IDE, AGP 8x,
Serial ATA, GTL, AGTL, DDR,
PCI, PCI express,
Industry’s direction on new buses.

METHOD OF GRADING

Coursework 20%
Project 25%
Midterm 25%
Final exam 30%
Total 100%

Resources:
  Presentation materials (Intel provided)
Industry Standards (PCI, IDE, USB, SCSI, GTL, etc.)
S. Hall, High-Speed Digital System Design, Wiley-Interscience, 2000. (Textbook).
H. Johnston, High Speed Digital Design – a Handbook of Black Magic, Prentice Hall, Inc., 1993.
David M. Pozar, Microwave Engineering, 2nd Edition, John Wiley & Sons Inc., 1998.

 


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