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Packet Filtering Based on IEEE Ethernet Address
The IXF440 was designed for Routing and Switching applications where the Switch ASIC or Network Processor performs the routing of packets. The IXF440 supports header preprocessing for early addressing filtering. Header preprocessing passes the packet header to the Switch ASIC or Network processor for filtering the incoming packet. The IXF440 does not support the assignment of individual IEEE Addresses per port.
IXF440 Reference Design
For IXF440 reference designs, customers can refer to the IXP1200 Evaluation Board. The IXP1200 Evaluation Board Reference design implements the IXF440 Octal Mac with the LTX9763 Hex MII Physical Layer device.
IXF440 Verilog Models for Simulation
To improve your time to market and minimize redesign activities, customers designing ASIC/FPGA interfaces to the IXF440 are encouraged to use Verilog model simulation. Verilog Models are available for the IXF440 in MTI, VCS and Verilog-XL formats. To obtain the Verilog models, please contact your local Intel Sales or Distributor representative.
Txrdy Stops Asserting
Txrdy of a port, will stop asserting when the Transmit FIFO is full or when two packets are present in the FIFO. The maximum number of packets in the IXF440 Transmit FIFO is two. You can determine the number of packets in the transmit FIFO by reading the IXF440 CSR register TMIT_STT. Packet transmission starts when EOP enters the transmit FIFO or when the packet threshold TX_TSHD_BOFF is met. For packet sizes greater than 64Bytes, you may be able to gain additional transmit FIFO efficiency by lowering the Transmit threshold TX_TSHD_BOFF.
Large Frame Support
The IXF440 supports large frames (Jumbo Packets) up to 32K Bytes. The maximum packets size is programmed by writing to the Max packet size register PKT_MAX_SIZE. It is possible to receive frames larger than the PKT_MAX_SIZE by programming the RX_FLT_MOD to “pass too long packets”. There are no limitations on the Transmit frame size.
Preventing Transmit FIFO Underflows
To prevent IXF440 Transmit FIFO underflows, applications should be designed with the highest possible IX Bus frequency, thus utilizing maximum IX Bus bandwidth. Additional Transmit underflow prevention can be obtained by increasing the value of the Transmit Threshold register (TX_TSHD_BOFF) to a level that maintains adequate data in the FIFO.
Can I disable the Receive Packet Status?
Receive Packet Status cannot be disabled on the IXF440.
Are software Drivers available for the IXF440?
Intel does not currently offer software Drivers for the IXF440.
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Intel® IXF440 Dual-Speed Multiport Ethernet MAC