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How do I read the configuration bytes?
On the A-step MCS® 251 microcontroller parts, the internal configuration bytes (CONFIG0:1) are located at 80h and 81h. This includes the ROM-less parts.
On the C-step of MCS 251 microcontroller ROM/OTP parts, the internal configuration bytes (UCONFIG0:1) are located at FF:FFF8h and FF:FFF9h.
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For any ROM-less C-step MCS 251 microcontroller, the configuration bytes are located externally in the first two bytes of the last 8 bytes, in external memory. Examples below are determined for the different size of memory interfaced:
| External Memory Size |
Number of
Address Line |
Address for
UCONFIG0 |
Address for
UCONFIG |
| 16K external EPROM |
14 |
3FF8H |
3FF9H |
| 32K external EPROM |
15 |
7FF8H |
7FF9H |
| 64K external EPROM |
16 |
FFF8H |
FFF9H |
| 128K external EPROM* |
17 |
1:FFF8H |
1:FFF9H |
| 256K external EPROM* |
18 |
3:FFF8H |
3:FFF8H |
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* Only applies to C-step MCS 251 microcontroller.
What are the differences between the MCS 251 microcontroller A-Stepping and C-Stepping?
The C-stepping of the device came out in May 1996; there are several differences. The configuration bytes CONFIG0 and CONFIG1 were renamed to UCONFIG0 and UCONFIG1. The user must program these configuration bytes. Please refer to the 8XC251SA/SB/SP/SQ User's Manual on Intel's Developer site, as well as the latest 8XC251SA/SB/SP/SQ Specification Update.
In the C-stepping of the MCS 251 microcontroller, a new address line on P1.7 has been added allowing for 18-bit addressing. This gives the MCS 251 microcontroller 256K of addressable memory as opposed to 128K on the A-stepping. There also have been numerous changes to the AC specs of the C-stepping, compared with the A-stepping. For example, signal Trhdz1 had a large change from 63ns in the A-stepping to 18ns (25ns typical) in the C-stepping.
What external memory location is accessed after configuration?
After configuration, the value on the address bus will be FF:0000. A maximum of 18 external address bits are accessible by the user. Depending on the RD1:0 bits in UCONFIG0; pins 16-18 will be used. The address accessed after configuration will be the lowest; 16, 17, or 18 bits of FF:0000, respectively.
Do any of the MCS 251 Microcontrollers come with a DAC or D/A converter?
No. To implement a Digital to Analog converter with a MCS 251 microcontroller an external peripheral will be required.
When Using the MCS 251 Microcontroller, 8xC251SX, does the stack grow up or down?
The stack grows in the upward direction. In other words, the stack pointer is incremented depending on the number of bytes pushed to the stack.
Should unused pins on the MCS 251 Microcontroller, 8xC251SX, be tied to Vcc or Vss?
Ports 1, 2 and 3 have fixed internal s and are referred to as quasi-bi-directional ports. Port 0 is a true bi-directional port (open drain); i.e., the port pins float when configured as input pins. If port 0 is not used, it is advisable to terminate the pins with pull-up resistors or pull the pins to ground in order to avoid floating. All other control pins have internal pull-up resistors. It is up to the user to determine if unused pins require a pull down to Vss. This may be advisable in a noisy environment.
What happens when an interrupt occurs when using an MCS 251 microcontroller?
A typical interrupt event chain occurs as follows. An internal or external device initiates an interrupt request signal. This signal, connected to an input pin and periodically sampled by the MCS 251 microcontroller, 8xC251SX, latches the event into a flag buffer. The interrupt handler compares the priority of the flag to the priority of other interrupts. A high priority causes the handler to set an interrupt flag. This signals the instruction execution unit to execute a context switch. This context switch breaks the current flow of instruction sequences. The execution unit completes the current instruction prior to a save of the program counter (PC) and reloads the PC with the start address of a software interrupt service routine (ISR). The software service routine executes assigned tasks and, as a final activity, performs a RETI (return from interrupt) instruction. This instruction signals completion of the interrupt, resets the interrupt-in-progress priority, and reloads the program counter. Program operation then continues from the original point of interruption. For more information refer to Interrupt System in the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User's Manual.
How does the pipeline on the MCS 251 microcontroller, 8xC251SX work?
The MCS 251 microcontroller, 8xC251SX, is a three stage pipeline machine. When the pipeline is full and code is executing from on-chip code memory, an instruction is completed every state time. When the pipeline is full and code is executing from external memory (with no wait states and no extension of the ALE signal), an instruction is completed every two state times. For more information, see the 8XC251SA/SB/SP/SQ User's Manual.
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Intel® MCS® 251 Microcontroller Components
