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Intel® IXB8055 UTOPIA/POS Reference Design
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| Intel® IXB8055 UTOPIA/POS Reference Design |
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The Intel® IXB8055 UTOPIA/POS Reference Design is a new addition to the already full-featured set of robust tools Intel offers its customers to accelerate time-to-market for Intel® IXP1200 based products. The IXB8055 Verilog code assists customers in bridging between the IX Bus and the Universal Test and Operations PHY Interface for ATM (UTOPIA) and ATM Packet-over-SONET (POS) interfaces.
A device loaded with the IXB8055 software translates IX Bus cycles on one side to UTOPIA bus cycles on the other side. On the IX side, the IXP1200 is responsible for initiating all transfers to the FIFOs. On the UTOPIA/POS side, the IXB8055 functions as an ATM layer device responsible for pushing and pulling either cells or packets (depending on configuration) to or from an ATM physical layer device.
The Intel IXP1200 offers an unmatched combination of flexible, programmable performance and very low power consumption. It is one of the first network processors in production and has been designed into a wide range of applications, including multi-service switches, routers, broadband access and wireless infrastructure systems. It is the first device to combine an embedded microprocessor core with six scalable microengines. This highly integrated processor satisfies rapidly changing and high data-rate performance requirements.
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Product features
- Proven design for high speed ATM integration
- Highly flexible building blocks for next generation networks
- Configurable to support industry standard UTOPIA Levels 1, 2 and 3
- Configurable support for Packet-over-SONET (POS) Levels 1, 2 and 3
- Supports multiple UTOPIA bus partitions in Direct Status Indication Mode (DSI) and Multiple PHY (MPHY) mode
- Supports four parity modes
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Highly flexible building blocks
Customers can use the IXB8055 Reference Design in a variety of ways. It has been implemented both as a behavioral design and as a Xilinx* Virtex-E XCV300E FPGA for customers' convenience. The extremely flexible software license allows customers to incorporate the IXB8055 into their own ASICs or into other components in their designs.
Product features
- The IXB8055 UTOPIA/POS Reference Design supports multiple cell sizes based on the UTOPIA 8, 16 or 32-bit bus width. Further, it supports two cell sizes per bus width.
- Each IX Bus interface supports separate 32-bit unidirectional transmit and receive busses and allows concurrent operation enabling multiple IXP1200 implementations.
- The UTOPIA/POS interface supports many DSI and MPHY modes. In DSI mode it can be partitioned four ways to support multiple UTOPIA levels: a single 32-bit bus, two independent 16-bit buses, four independent 8-bit buses, and a single 16-bit bus together with two 8-bit buses. In MPHY mode all ports share an interface that can be partitioned as a 32-bit, a 16-bit or an 8-bit bus.
- The UTOPIA/POS interface supports two decode response times - the number of clock cycles it takes a device to respond to the initiating signal.
- In order to minimize design complexity and gate count, the IXB8055 software is configured via strap pins eliminating the need for custom programming.
- The IXB8055 supports four parity modes - no parity, EVEN, ODD and dual - for flexibility to support custom configurations.
- The IXB8055 supports POS Level 3 exclusive of in-band addressing.
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