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Home ›  Products ›  Networking & Communications ›  Ethernet  82546EB
Intel® 82546EB Dual Port Gigabit Ethernet Controller
Overview
Key Applications | Features and Benfits | Characteristics

82546EB The Intel® 82546EB Dual Port Gigabit Ethernet Controller is a single, compact component with two full Gigabit Ethernet MAC and PHY layer functions. Packaged in a 21x21 mm PBGA, the Intel 82546EB Dual Port Gigabit Ethernet controller provides dual port functionality without additional board space requirements for the component and enables a dual port Gigabit Ethernet implementation in a very small area.

The Intel 82546EB integrates Intel's fourth generation Gigabit MAC design with fully integrated, physical-layer circuitry to provide two standard IEEE 802.3 Ethernet interfaces for 1000Base-T, 100Base-TX, and 10Base-T applications (802.3, 802.3u, 802.3ab). The controller is capable of transmitting and receiving two channels of data at 1000 Mb/s, 100 Mb/s, or 10 Mb/s data rates. For fiber optic applications, the Intel 82546EB's two integrated SERDES support 1000BASE-SX and 1000BASE-LX (802.3z). In addition, the controller provides a single, direct Peripheral Component Interconnect (PCI) 2.2 and PCI-X 1.0a compliant bus that operates as a single multi-function device on the bus at clock frequencies up to 133 MHz.

The Intel 82546EB's on-board SMBus port enables enhanced manageability and system health monitoring via the LAN. With SMBus, management packets can be routed to or from a management processor. The SMBus port enables industry standards such as IPMI (Intelligent Platform Management Interface) to be implemented with the Intel 82546EB. In addition, ASF 1.0 (Alert Standard Format) standard circuitry provides alerting and remote control capabilities with standardized interfaces.

The Intel® 82546EB Gigabit Ethernet Controller architecture is optimized to deliver both high performance and PCI/PCI-X bus efficiency. Using state logic design with a pipelined DMA Unit and 128 bit wide buses for the fastest performance, the Intel 82546EB controller handles Gigabit Ethernet traffic with low network latency and minimal internal processing overhead. The controller's architecture includes independent transmit and receive queues to limit PCI bus traffic, and a PCI interface that maximizes the use of bursts for efficient bus usage. The Intel 82546EB Gigabit Ethernet Controller prefetches up to 64 packet descriptors in a single burst for efficient PCI-bandwidth usage. Two 64 KB on-chip packet buffers maintain superior performance as available PCI bandwidth changes. Advanced interrupt moderation hardware manages interrupts generated by the Intel 82546EB controller to further improve system efficiency. In addition, using hardware acceleration, the controller also offloads tasks from the host processor, such as TCP/UDP/ IP checksum calculations and TCP segmentation.
Key Applications
The Intel 82546EB Gigabit Ethernet Controller is designed for use in the following applications:

LAN on Motherboard (LOM) in dense, space constrained systems such as rack-mounted servers and high-density blade servers
Communications platforms using dual Gigabit Ethernet on the backplane (PICMG 2.16 compliant or 1000BASE-SX)
Internet infrastructure devices with high-speed requirements and limited board real estate, such as switches, routers, and load balancers
Features and Benefits
PCI/PCI-X Features
133MHz PCI-X bus Supports bandwidth to allow wire-speed performance of two Gigabit Ethernet connections
Multi-function PCI device
One electrical load on the PCI/PCI-X bus
Lowest latency solution - a PCI/PCI-X bridge component is not required to implement a dual port design
PCI revision 2.2, 32/64 bit, 33/66 MHz
Application flexibility in LOM or embedded use
64-bit addressing for systems with more than 4GB of physical memory
Algorithms that optimally use advanced PCI MWI, MRM, MRL and PCI-X MRD, MRB, and MWB commands Efficient bus operations
MAC Specific Features
Dual 64KB configurable RX and TX packet FIFOs No external FIFO memory requirements
FIFO size tunable to the application
Low-latency transmit and receive queues Network packets handled without waiting or buffer overflow
IEEE 802.3x compliant flow control support with software controllable pause times and threshold values
Control over the transmission of Pause frames through software or hardware triggering
Reduced frame loss due to receive FIFO overrun
Caches up to 64 packet descriptors in a single burst Efficient PCI-bandwidth usage
Programmable host memory receive buffers (256B to 16KB)
Programmable cache line size from 16B to 256B
Efficient usage of PCI bandwidth
128-bit internal data path architecture
Low latency data handling
Superior DMA transfer rate performance
Ring descriptor buffer structure with cache that promotes long PCI bursts to fetch descriptors Efficient system memory and PCI bandwidth usage
Dual Internal Serializer-Deserializers (SERDES)
Enables dual Fiber Gigabit Ethernet designs
Solution for server blade backplane connections
Facilitates easier routing (improved thermals) and requires less power
Gigabit PHY Specific Features
Two integrated PHYs for 10/100/1000 Mb/s full and half duplex operation Reduced board space and lower power dissipation compared to multi-chip MAC/PHY solutions
IEEE 802.3ab Auto-Negotiation Automatic link configuration including speed, duplex, and flow control
Proven PHY technology compatible with IEEE 802.3ab Robust operation over the installed base of CAT-5 twisted pair cabling at lengths greater than 100m
State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation, baseline wander cancellation Robust 1000 Mb/s performance in noisy environments and despite severe cable installation problems
PHY detects polarity, MDI-X, 2 pair vs. 4 pair cables, and cable length
Easier network installation and maintenance
No need to know the difference between crossover and non-crossover cables
End to end wiring tolerance
GMII and Ten Bit Interface (TBI) Gigabit Ethernet design flexibility
Host Offloading Features
Transmit TCP segmentation Increased throughput and lower CPU utilization. Compatible with large send offload feature found in Windows*2000 and Windows* XP
IP, TCP, and UDP checksum off-loading capabilities on RX and TX Reduced host CPU utilization
Advanced packet filtering
16 exact matched (unicast or multicast)
4096-bit hash filter for multicast frames
Promiscuous (unicast/multicast) transfer mode
Optional filtering of erred frames
IEEE 802.1Q VLAN support with VLAN tag insertion and stripping and packet filtering for up to 4096 VLAN tags Enables IT staff to easily create multiple virtual LAN segments
Descriptor ring management hardware for TX and RX Optimized fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage
Jumbo frame support up to 16KB High throughput for large data transfers on networks supporting jumbo frames
Interrupt Management Features
Interrupt moderation controls - bring Intel's experience in Fast Ethernet adaptive technology to Gigabit Ethernet performance levels
Reduces the number of interrupts generated by receive and transmit operations
Maximizes system performance and throughput
Small Packet Interrupt Fast detection of TCP ACKs for improved small packet throughput
Manageability Features (available on both ports)
On-chip SMBus 2.0 port
Enables IPMI, and ASF implementations
Allows packets to be routed to and from either LAN port and a server management processor
ASF 1.0 alerting Provides alerting and remote control capabilities with standardized interfaces
Pre-boot eXecution Environment (PXE) 2.1 flash interface support (32-bit and 64-bit) Local flash interface for a PXE image
Designed for PCI Power Management v1.1/ACPIv2.0 PCI power management capability requirements for PC and embedded applications
SNMP and RMON statistic counters Easy system monitoring with industry standard consoles
SDG3.0, WfM 2.0, PC2001 Compliance Remote network management capabilities via DMI 2.0 and SNMP software
Wake on LAN (WoL) support Packet recognition and wakeup for network adapter and LOM applications without software configuration
Automatic link speed switching from 1000 Mb/s down to 10 or 100 Mb/s in standby
Low power in standby states
Supports power down states without software assistance
Diagnostic capabilities including loop back, reporting cable length, cable polarity, number of symbol errors, and incorrectly punched down cables Provide IT managers with meaningful information used to analyze the health and state of their LAN infrastructure
Additional Device Features
Eight programmable LED outputs
Indications for link speed, activity, duplex, collisions, pause by flow control, PCI speed, PCI width, and port ID on each port
Allows design customization without affecting software drivers
Eight software definable pins Additional flexibility for LED's or other low speed I/O
Internal PLL for clock generation can use a 25 MHz crystal or a 25 MHz oscillator Lower component count and system cost
JTAG (IEEE 1149.1) Test Access Port built in Simplified testing using boundary scan
On-chip power regulator control circuitry
Fewer on-board power supply regulators
Simplified power supply design
Characteristics
Electrical
PCI Signaling
Power Dissipation
3.3V and 5V
3.5W (1.75W/port) (typical)
Environmental
Operating temperature
Storage temperature
0° C to 70° C (maximum), does not require a heat sink or forced airflow
-65° C to 140° C
Physical
Package
Footprint compatible with Intel® 82544GC and Intel® 82545EM single port Gigabit Ethernet controllers
364 pin PBGA, 1mm ball pitch
21 X 21 mm (Saves critical space on LOM board designs)
Enables a single port or dual port implementation on the same board

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