| PCI/PCI-X Features |
| 133MHz PCI-X bus |
Supports bandwidth to allow wire-speed performance of two Gigabit Ethernet connections |
| Multi-function PCI device |
Lowest latency solution - a PCI/PCI-X bridge component is not required to implement a dual port design |
| PCI revision 2.3, 32/64-bit, 33/66MHz |
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Application flexibility in LOM or embedded use |
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64-bit addressing for systems with more than 4GB of physical memory |
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| Gigabit MAC/PHY/SerDes Advanced Features |
| 64KB configurable RX and TX packet FIFOs |
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No external FIFO memory requirements |
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FIFO size tunable to the application |
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| IEEE 802.3x compliant flow control support with software controllable thresholds |
Reduced frame loss due to receive FIFO overrun |
| Caches up to 64 packet descriptors in a single burst |
Efficient PCI-bandwidth usage |
| Programmable host memory receive buffers (256B to 16KB) |
Efficient usage of PCI bandwidth |
| Interrupt moderation controls |
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Reduces the number of interrupts generated by receive and transmit operations |
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Improves throughput performance and CPU utilization |
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| Jumbo frame support up to 16KB |
High throughput for large data transfers on networks supporting jumbo frames |
| IEEE 802.1Q VLAN support with VLAN tag insertion and stripping and packet filtering for up to 4096 VLAN tags |
Enables IT staff to easily create multiple virtual LAN segments |
| Integrated PHYs for 10/100/1000Mb/s full- and half-duplex operation |
Reduced board space and lower power dissipation |
| IEEE 802.3ab Auto-Negotiation |
Automatic link configuration including speed, duplex, and flow control |
| State-of-the-art DSP architecture implements digital adaptive equalization, echo, cross-talk and baseline wander cancellation |
Robust 1000Mb/s performance in noisy environments and despite severe cable installation problems |
| PHY detects polarity, MDI-X, 2 pair vs. 4 pair and 3 pair vs. 4 pair cables |
Easier network installation and maintenance |
| Integrated Serializer-Deserializers (SerDes) PICMG 3.1 compliant |
Solution for server blade backplane connections and Fiber Gigabit Ethernet |
| Host Offloading Features |
| Transmit TCP segmentation, and IP, TCP, and UDP checksum off-loading capabilities on RX and TX |
Increased throughput and lower CPU utilization. Compatible with large send offload feature found in Windows* 2000 and Windows* XP |
| Advanced packet filtering |
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16 exact matched (unicast or multicast) |
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Promiscuous (unicast/multicast) transfer mode |
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| Manageability Features (available on both ports) |
| On-chip SMBus 2.0 port |
Enables IPMI, and ASF implementations |
| ASF 1.0 |
Provides alerting and remote-control capabilities with standardized interfaces |
| Compliance with PCI Power Management v1.1/ACPI v2.0 |
PCI power management capability requirements for PC and embedded applications |
| Wake on LAN (WoL) support |
Packet recognition and wakeup for network adapter and LOM applications |
| Automatic link speed switching from 1000Mb/s down to 10 or 100Mb/s in standby |
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Low power in standby states |
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Supports power-down states without software assistance |
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| Additional Features |
| Four programmable LED outputs ID on each port |
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Indications for link speed, activity, duplex, collisions, pause by flow control, PCI speed, PCI width, and port ID on each port |
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Allows design customization without affecting software drivers |
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| On-chip power regulator control circuitry |
Simplified power supply design |