Products
82544 Gigabit Ethernet Controllers with Integrated PHY
Overview
Key Applications | Block Diagram | Features and Benfits | Characteristics

82544 Family The Intel® 82544EI and 82544GC Gigabit Ethernet Controllers are integrated, third-generation, Ethernet-LAN components, capable of supporting 1000 Mb/s, 100 Mb/s, and 10 Mb/s data rates. These single-chip devices manage both the MAC and PHY layer functions, and are optimized for LAN on Motherboard (LOM) designs, enterprise networking, and Internet appliances that use the Peripheral Component Interconnect (PCI) or PCI-X bus. The controllers provide a direct 32/64 bit, 33/66 MHz interface to the PCI bus that supports the PCI Local Bus Specification (revision 2.2), as well as the emerging PCI-X extension to the PCI Local Bus (revision 1.0a) at clock rates up to 133 MHz.

The Intel 82544EI and 82544GC Gigabit Ethernet Controllers provide an interface to the host processors by using on-chip command and status registers and a shared host-memory area. The controller's descriptor ring management architecture is optimized to deliver both high performance and PCI/PCI-X bus efficiency. Using hardware acceleration, the controllers can offload various tasks from the host processor, such as TCP/UDP/ IP checksum calculations and TCP segmentation. The Intel 82544EI and 82544GC Gigabit Ethernet Controllers cache up to 64 packet descriptors in a single burst for efficient PCI-bandwidth usage while the large 64KB on-chip packet buffer maintains superior performance as available PCI bandwidth descriptors change.

Fully integrated physical-layer circuitry provides a standard IEEE 802.3 Ethernet interface for 1000Base-T, 100Base-TX, and 10Base-T applications (802.3ab, 802.3u, 802.3). And, with the addition of an appropriate serializer/deserializer (SERDES), the Intel 82544EI and 82544GC Gigabit Ethernet Controllers alternatively provide an Ethernet interface for 1000Base-SX or LX applications (802.3z).
Key Applications
The Intel 82544EI and 82544GC Gigabit Ethernet Controllers are designed for use in the following applications:

LAN on Motherboard (LOM) for servers and workstations
Industrial PCs including Compact-PCI and PMC designs
Embedded designs that use a PCI bus (such as Ethernet switches, routers, firewalls, NAS filers and other server appliances)
The 82544EI and 82544GC single-chip Gigabit Ethernet (MAC/PHY) solutions take up less space, making it easier to provide high speed, network connections as a standard part of a system.
Block Diagram
82544 Diagram

Features and Benefits
PCI/PCI-X Features
PCI revision 2.2 at 32/64 bit, 33/66 MHz
Application flexibility in LOM, embedded, or NIC use
64-bit addressing for systems with more than 4GB of physical memory
PCI-X, rev.1.0a compliant host interface at clock rates up to 133 MHz Optimized server bus performance
Algorithms that optimally use advanced PCI MWI, MRM, MRL and PCI-X MRD, MRB, and MWB commands Efficient bus operations
Network Interface (MAC)
Low latency transmit and receive queues Network packets handled without waiting or buffer overflow
TBI interface, in addition to internal PHY, for IEEE 802.3z full duplex operation with SERDES Single device to interface with fiber or CAT-5 twisted pair transmission mediums
IEEE 802.3x compliant flow control support with software controllable pause times and threshold values Control over the transmission of Pause frames through software or hardware triggering
Internal Transceiver (PHY) Features
Integrated PHY for 10/100/1000 Mb/s full and half duplex operation Reduced board space and lower power dissipation compared to multi-chip MAC/PHY solutions
IEEE 802.3ab Auto-Negotiation Automatic link configuration including speed, duplex, and flow control
Proven PHY compatible with IEEE 802.3ab Robust operation over the installed base of CAT-5 twisted pair cabling
State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation
Robust performance in noisy environments
Tolerance of common electrical signal impairments
Host Offloading Features
RX and TX IP and TCP/UDP checksum off-loading capabilities Reduced host CPU utilization
Transmit TCP segmentation offloads host by sending up to 64K of block TCP data to network controller
Increased throughput and lower CPU utilization
Compatible with large send offload feature found in Windows* XP
Advanced packet filtering
16 exact matched (unicast or multicast)
4096-bit hash filter for multicast frames
Promiscuous (unicast/multicast) transfer mode
Optional filtering of erred frames
IEEE 802.1Q VLAN support
VLAN tag insertion and stripping
Packet filtering for up to 4096 VLAN tags
Descriptor ring management hardware for TX and RX Optimized fetching and write-back mechanisms for efficient system memory and PCI banwidth usage
16 KB jumbo frame support High throughput for large data transfers on compatible network segments
Interrupt coalescing (more than one packet per interrupt) Reduced interrupts generated by RX and TX operations, increasing throughput
Memory
Programmable host memory receive buffers (256B to 16KB)
Programmable cache line size from 16B to 256B
Efficient usage of PCI banwidth
128-bit internal data path architecture Superior DMA transfer rate performance
Independent transmit and receive queues Enables simultaneous access by multiple CPUs
64KB of configurable RX and TX Packet FIFOs No external FIFO memory requirements
Management Features
SDG3.0, WfM 2.0, PC2001 Compliance Remote network management capabilities via DMI 2.0 and SNMP software
Pre-boot eXecution Environment (PXE) Flash interface support Local flash interface for a PXE image
ACPI, PCI Power Management, Version 1.1 compliance PCI power management capability requirements for NIC and LOM applications
SNMP and RMON statistic counters Ease of monitoring system status
Wake on LAN* support Packet recognition and wakeup for NIC and LOM applications without software configuration
Additional Items
Six activity and link indication outputs that directly drive LEDs Indications for Link, RX, TX, and 10, 100, 1000 Mb/s
PHY detects polarity, MDI-X, and cable lengths. Auto MDI, MDI-X at all speeds
Easier network installation and maintenance
No need to know the difference between crossover and non-crossover cables
End to end wiring tolerance
Internal PLL for clock generation using a 25 MHz crystal or a 25 MHz oscillator Lower component count and cost
JTAG (IEEE 1149.1) Test Access Port built in Simplified testing using boundary scan

Characteristics
Electrical
PCI Signaling
Power Dissipation
3.3V or 5V environments
2.1W (typical), low power and heat - optimized for space constrained applications
Environmental
Operating temperature

Storage temperature
82544EI: 0 C to 70 C (maximum); 82544GC: 0 C to 55 C (maximum), does not require a heat sink or forced airflow
-65 C to 140 C
Physical
Two package sizes to simplify LOM and embedded board designs
82544EI: 416 pin PBGA, 27 X 27 mm
82544GC: 364 pin TFBGA, 21 X 21 mm

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