| PCI Bus Features |
| PCI revision 2.3, 32-bit, 33/66MHz |
Application flexibility in LOM or embedded use |
| CLKRUN# Signal |
PCI clock suspension for low-power mobile design |
| Gigabit MAC/PHY Advanced Features |
| 64KB configurable RX and TX packet FIFO |
FIFO size tunable to the application |
| IEEE 802.3x-compliant flow-control support with software-controllable thresholds |
Reduced frame loss due to receive FIFO overrun |
| Programmable host memory receive buffers (256B to 16KB) |
Efficient usage of system resources |
| IEEE 802.3ab Auto-Negotiation |
Automatic link configuration including speed, duplex, and flow control |
| State-of-the-art DSP/analog architecture |
Implements digital adaptive equalization, echo, cross-talk and baseline wander cancellation |
| PHY detects polarity, 2 pair vs. 4 pair cables |
Easier network installation and maintenance |
| Host Offloading Features |
| Transmit TCP segmentation IP, TCP, and UDP checksum offloading |
Increased throughput and lower CPU utilization. Compatible with large send offload on RX and TXfeature found in Windows* 2000 and Windows* XP |
| IEEE 802.1Q VLAN support with VLAN tag insertion and stripping and packet filtering for up to 64 simultaneous VLANs |
Enables IT staff to easily create multiple virtual LAN segments |
| Jumbo frame support up to 16KB |
High throughput for large data transfers on networks supporting jumbo frames |
| Interrupt moderation controls |
Reduces the number of interrupts generated by receive and transmit operations |
| Manageability Features |
| On- chip SMBus 2.0 port |
Enables IPMI and ASF implementations |
| ASF 1.0 and 2.0 |
Provides advanced alerting and remote control capabilities with industry |
| Compliance with PCI Power Management v1.1/ACPI v2.0 |
PCI power management capability requirements for PC and embedded applications |
| Wake on LAN* (WoL) support |
Packet recognition and wakeup for network adapter and LOM applications without software configuration |
| Automatic link speed switching from 1000Mb/s down |
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Supports power-down states without software assistance |
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Low power in standby states to 10 or 100Mb/s in standby |
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| Smart Power Down mode when no signal is detected on the wire |
Enables very low power mobile or battery |
| Power Save mode switches link speed from 1000Mb/s down to 10 or 100Mb/s when on battery power |
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Manages power consumption based on power source |
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Longer battery life for battery-powered implementations |
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| Additional Device Features |
| Four programmable LED outputs |
Customizable indications for link speed, activity, duplex, collisions, and port ID on each port |
| On-chip power regulator control circuitry |
Simplified low-cost power supply design |
| BIOS LAN Disable Pin |
Enables low-power LAN disable for LOM applications |
82541EI
The Intel® 82541EI Gigabit Ethernet Controller provides optimized Gigabit networking for PCI designs. This highly efficient controller, with enhanced power management, consumes less than 1.0W of power at Gigabit speeds. When no signal is detected on the wire, the controller reduces power consumption by switching to 100 or 10 and powering down the physical-layer circuitry (PHY). When a signal is detected, the controller automatically negotiates the connection to Gigabit, if available.