| PCI Bus Features |
| PCI revision 2.3, 32-bit, 33/66MHz |
Application flexibility in LOM or embedded use |
| CLKRUN# Signal |
PCI clock suspension for low power mobile design |
| Cardbus Information Services (CIS) Pointer |
Enables CardBus operation |
| MAC Specific Features |
| 64KB configurable RX and TX packet FIFO |
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No external FIFO memory requirements |
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FIFO size tunable to the application
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| Low-latency transmit and receive queues |
Network packets handled without waiting or buffer overflow |
| IEEE 802.3x compliant flow-control support with software-controllable pause times and threshold values |
Reduced frame loss due to receive FIFO overrun |
| Caches up to 64 packet descriptors in a single burst |
Efficient PCI-bandwidth usage |
| Programmable host memory receive buffers (256B to 16KB); Programmable cache line size from 16B to 256B |
Efficient usage of PCI bandwidth |
| Gigabit PHY Specific Features |
| Integrated PHYs for 10/100/1000 Mb/s full-and half-duplex operation |
Reduced board space and lower power dissipation |
| IEEE 802.3ab Auto-Negotiation |
Automatic link configuration including speed, duplex, and flow control |
| Proven PHY technology compatible with IEEE 802.3ab |
Robust operation over the installed base of CAT-5 twisted-pair cabling at lengths greater than 100m |
| State-of-the-art DSP architecture implements digital adaptive equalization, echo, cross-talk and baseline wander cancellation |
Robust 1000 Mb/s performance in noisy environments and despite severe cable installation problems |
| PHY detects polarity, MDI-X, 2 pair vs. 4 pair cables, and cable length |
Easier network installation and maintenance |
| Host Offloading Features |
| Transmit TCP segmentation, IP, TCP, and UDP checksum off-loading capabilities on RX and TX |
Increased throughput and lower CPU utilization. Compatible with large send off-load feature found in Windows* 2000 and Windows* XP |
| Advanced packet filtering |
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16 exact matched (unicast or multicast) |
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Promiscuous (unicast/multicast) transfer mode |
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| IEEE 802.1Q VLAN support with VLAN tag insertion and stripping and packet filtering for up to 4096 VLAN tags |
Enables IT staff to easily create multiple virtual LAN segments |
| Descriptor ring management hardware for TX and RX |
Improved fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage |
| Jumbo frame support up to 16KB |
High throughput for large data transfers on networks supporting jumbo frames |
| Interrupt moderation controls |
Reduces the number of interrupts generated by receive and transmit operations |
| Manageability Features |
| On-chip SMBus 2.0 port |
Enables IPMI and ASF implementations |
| ASF 1.0 alerting |
Provides alerting and remote control capabilities with standardized interfaces |
| Compliance with PCI Power Management v1.1/ACPI v2.0 |
PCI power management capability requirements for PC and embedded applications |
| Wake on LAN™ (WoL)* support |
Packet recognition and wakeup for network adapter and LOM applications without software configuration |
| Automatic link speed switching from 1000 Mb/s down to 10 or 100 Mb/s in standby |
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Low power in standby states |
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Supports power-down states without software assistance |
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| Smart Power Down mode when no signal is detected on the wire |
Enables very low power mobile or battery powered implementations |
| Two-pair and three-pair downshift |
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Assures link under adverse cable configurations |
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Supports modular hardware accessories |
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| Power Save mode switches link speed from 1000 Mb/s down to 10 or 100 Mb/s when on battery power |
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Manages power consumption based on power source |
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Longer battery life for battery powered implementations |
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| Additional Device Features |
| Four programmable LED outputs |
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Indications for link speed, activity, duplex, collisions, pause by flow control, PCI speed, PCI width, and port ID on each port |
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Allows design customization without affecting software drivers |
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| Internal PLL for clock generation using a 25 MHz crystal or a 25 MHz oscillator |
Lower component count and cost |
| On-chip power regulator control circuitry |
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Fewer on-board power supply regulators |
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Simplified power supply design |
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| LAN Disable Pin |
Enables low power LAN disable for LOM applications |
82540EP
Intel® 82540EP Gigabit Ethernet Controller is a single, compact component with integrated MAC and PHY layer functions. Packaged in a 15x15mm TFBGA, the Intel 82540EP Gigabit Ethernet Controller is footprint compatible with the Intel® 82551QM, 88551ER, 82562EZ and 82562EX Fast Ethernet Controllers, allowing for a flexible, Gigabit Ethernet or 10/100 Ethernet design.