| PCI Bus Features |
| PCI revision 2.2, 32-bit, 33/66 MHz |
Application flexibility in LOM or embedded use |
| Algorithms that optimally use advanced PCI MWI, MRM, MRL commands |
Efficient bus operations |
| MAC Specific Features |
| 64KB configurable RX and TX packet FIFO |
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No external FIFO memory requirements |
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FIFO size tunable to the application |
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| Low-latency transmit and receive queues |
Network packets handled without waiting or buffer overflow |
| IEEE 802.3x compliant flow control support with software controllable pause times and threshold values |
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Control over the transmission of Pause frames through software or hardware triggering |
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Reduced frame loss due to receive FIFO overrun |
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| Caches up to 64 packet descriptors in a single burst |
Efficient PCI-bandwidth usage |
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Programmable host memory receive buffers (256B to 16KB) |
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Programmable cache line size from 16B to 256B |
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Efficient usage of PCI bandwidth |
| 128-bit internal data path architecture |
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Low latency data handling |
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Superior DMA transfer rate performance |
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| Optimized descriptor fetching and write-back mechanisms |
Efficient system memory and PCI bandwidth usage |
| Gigabit PHY Specific Features |
| Integrated PHY for 10/100/1000 Mb/s full and half duplex operation |
Reduced board space and lower power dissipation compared to multi-chip MAC/PHY solutions |
| IEEE 802.3ab Auto-Negotiation |
Automatic link configuration including speed, duplex, and flow control |
| Proven PHY technology compatible with IEEE 802.3ab |
Robust operation over the installed base of CAT-5 twisted pair cabling at lengths greater than 100m |
| State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation, baseline wander cancellation |
Robust 1000 Mb/s performance in noisy environments and despite severe cable installation problems |
| PHY detects polarity, MDI-X, 2 pair vs. 4 pair cables, and cable length |
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Easier network installation and maintenance |
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No need to know the difference between crossover and non-crossover cables |
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End to end wiring tolerance |
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| Host Offloading Features |
| Transmit TCP segmentation |
Increased throughput and lower CPU utilization. Compatible with large send offload feature found in Windows*2000 and Windows* XP |
| IP, TCP, and UDP checksum off-loading capabilities on RX and TX |
Reduced host CPU utilization |
| Advanced packet filtering |
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16 exact matched (unicast or multicast) |
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4096-bit hash filter for multicast frames |
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Promiscuous (unicast/multicast) transfer mode |
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Optional filtering of erred frames |
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| IEEE 802.1Q VLAN support with VLAN tag insertion and stripping and packet filtering for up to 4096 VLAN tags |
Enables IT staff to easily create multiple virtual LAN segments |
| Descriptor ring management hardware for TX and RX |
Optimized fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage |
| Jumbo frame support up to 16KB |
High throughput for large data transfers on networks supporting jumbo frames |
| Interrupt Management Features |
| Interrupt moderation controls |
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Reduces the number of interrupts generated by receive and transmit operations |
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Maximizes system performance and throughput |
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| Small Packet Interrupt |
Fast detection of TCP ACKs for improved small packet throughput |
| Manageability Features |
| On-chip SMBus 2.0 port |
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Enables IPMI, and ASF implementations |
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Allows packets to be routed to and from either LAN port and a server management processor |
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| ASF 1.0 alerting |
Provides alerting and remote control capabilities with standardized interfaces |
| Pre-boot eXecution Environment (PXE) 2.1 |
Compatible with Intel® Boot Agent software |
| Compliance with PCI Power Management v1.1/ACPI v2.0 |
PCI power management capability requirements for PC and embedded applications |
| SNMP and RMON statistic counters |
Easy system monitoring with industry standard consoles |
| SDG3.0, WfM 2.0, PC2001 Compliance |
Remote network management capabilities via DMI 2.0 and SNMP software |
| Wake on LAN (WoL) support |
Packet recognition and wakeup for network adapter and LOM applications without software configuration |
| Automatic link speed switching from 1000 Mb/s down to 10 or 100 Mb/s in standby |
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Low power in standby states |
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Supports power down states without software assistance |
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| Smart Power Down mode when no signal is detected on the wire |
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90% of chip powered down until activity on LAN is detected |
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Enables very low power mobile or battery powered implementations |
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| Diagnostic capabilities including loop back, reporting cable length, cable polarity, number of symbol errors, and incorrectly punched down cables |
Provide IT managers with meaningful information used to analyze the health and state of their LAN infrastructure |
| Additional Device Features |
| Four programmable LED outputs |
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Indications for link speed, activity, duplex, collisions, pause by flow control, PCI speed, PCI width, and port ID on each port |
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Allows design customization without affecting software drivers |
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| Four software definable pins |
Additional flexibility for LED's or other low speed I/O |
| Internal PLL for clock generation can use a 25 MHz crystal or a 25 MHz oscillator |
Lower component count and system cost |
| JTAG (IEEE 1149.1) Test Access Port built in |
Simplified testing using boundary scan |
| On-chip power regulator control circuitry |
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Fewer on-board power supply regulators |
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Simplified power supply design |
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82540EM
The Intel® 82540EM Gigabit Ethernet Controller is a single, compact component with integrated Gigabit Ethernet MAC and PHY layer functions. Packaged in a 15x15 mm TFBGA, the Intel 82540EM Gigabit Ethernet controller is footprint compatible with the Intel® 82551QM and 82551ER Fast Ethernet Controllers (same package size, same number and pattern of pins and similar signal layout), allowing for a flexible, Gigabit Ethernet or 10/100 Ethernet design.
