Architectural Description of Embedded Signal Processors and DSP Algorithm Implementation for the 80C296SA
High speed calculations consisting of arithmetic and fast input/output operations are handled well by standard embedded signal processors. This paper describes the pipeline architecture of a high performance embedded signal processor and the register to register architectural feature that speeds up processing and minimizes context switching. To summarize the architectural features, the design and implementation of a FIR filter and PID routines are described.
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