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MCS® 51 FX/GX Microcontroller New Interrupt Priority Register
- INTEL REF NO: [2019][MIC1390]EFG
- PRODUCTS COVERED: 87C51FC, 8XC54
- DATE/VERSION: 07/30/90; Ver 1.00
- RELATED INFO: Data Book
- KEYWORDS: MCS-51 FX INTERRUPT
Abstract
This TechBit clarifies the name and function of the new interrupt priority register on the FX core.
New Interrupt Priority Register Name
There has been some confusion about the name and function of the new interrupt priority register resident on the FX core.
Figure 1 shows the correct naming convention for the register.
| IPH |
| (0B7H) |
- |
PPCH |
PT2H |
PSH |
PT1H |
PX1H |
PT0H |
PX0H |
Figure 1
The new register becomes the MSB of the priority select bits and the existing IP register acts as the LSB. This scheme maintains compatibility with the rest of the MCS-51 family.
Table 1 shows the bit values and the priority level associated with each combination.
Priority Select Bits MSB LSB
| IPH.X |
IP.X |
(X is the bit position 0 - 6) |
| 0 |
0 |
Interrupt Priority level 0 (lowest) |
| 0 |
1 |
Interrupt Priority level 1 |
| 1 |
0 |
Interrupt Priority level 2 |
| 1 |
1 |
Interrupt Priority level 3 (highest) |
Table 1
The IP1 bit functions defined at the bottom of the Interrupt Priority Register Table should also be changed to match the IPH (0B7H) names from above.
- PC_1 should be PCCH
- PC2_1 should be PT2H
- PS_1 should be PSH
- PT1_1 should be PT1H
- PX1_1 should be PX1H
- PT0_1 should be PT0H
- PX0_1 should be PX0H
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