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One of the innovative features of the MCS® 251 microcontrollers is page mode. Page mode increases performance by up to 2X by reducing the time for external code fetches. |
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Under page mode configuration, the data base (D7:0) is multiplexed with a higher address byte (A15:8) on port 2 instead of being multiplexed with a lower address byte (A7:0) on port 0. With this configuration, the controller is able to fetch an instruction from external memory in two clocks instead of four. The MCS 251 microcontrollers default to non-page mode for pin compatibility |
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with the MCS® 51 microcontroller. To enable page mode, users have to configure or program the "page" bit in the Uconfig0 configuration byte to zero. Page mode does not affect internal code fetches. |
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The first code fetch to a 256-byte "page" of memory always uses a four-clock bus cycle. Subsequent successive code fetches to the same page (page hits) require only a two-clock bus cycle. When a subsequent fetch is to a different page (a page miss), it again requires a four-clock bus cycle. |
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The page-miss cycle is the same as a code fetch cycle in non-page mode. For the page-hit cycle, the upper eight address bits are the same as for the preceding cycle. However, a page hit reduces the available address access time by two clocks. Therefore, faster memories may be required to support page mode. |
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