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Features |
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Benefits |
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New core architecture |
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Up to 15X performance increase using new MCS 251 microcontroller instructions |
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Significantly reduce RFI |
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Increase efficiency and support of C language programming |
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Binary code and pin compatible with MCS 51 microcontroller |
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Hardware investment protected |
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Reduce development time with backward compatible MCS 51 microcontroller instruction set |
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8 Kbytes/16 Kbytes on-chip ROM/OTPROM or ROMless version |
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Flexibility in using different memory options in development and production |
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Programmable Counter Array (PCA) supports
-Real-time capture and compare
-High speed output
-PWM |
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Flexibility and performance enhancement in real-time control applications such as:
-Measurement of duty cycle, phase difference and frequency
-Real-time interrupt generation and output toggling
-Adjustable duty cycle generation |
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Hardware watchdog timer |
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Increased system reliability |
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Page mode configuration |
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Increases the performance for external instruction fetch by 2X |
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Programmable wait states (0-3) configuration and external wait pin capability |
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Flexibility in external memory and peripheral interface
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Allows the use of either fast or slow memory |
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Support seven interrupt sources, each with four interrupt priority levels |
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Increased flexibility for event control applications |
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256 Kbytes external memory space |
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Increased capability and flexibility to handle large software requirements |
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512/1 Kbyte on-chip RAM |
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Increased internal memory capacity for data manipulation and C language support |
