186EX to PCMCIA Interface

1. Abstract:
This paper discusses an application of Series 2 Flash memory cards in an embedded 186 design. The series 2 flash memory cards could be used for data as well as code storage. This paper describes a generalized, low cost design approach to interfacing Series 2 Flash memory cards to the embedded 186 based systems to vastly enhance the system's data storage capability. Also, this would allow the designer to broaden the scope of his application.

2. Introduction:
Engineers face a growing need to produce ROMable code for Intel architecture microprocessors. The low cost, high quality, and availability of standard DOS tools make them attractive candidates as ROMable-code generators [1]. Even though most of the embedded systems do not run under DOS, it would be easier, cheaper and time to market could be reduced considerably if DOS based PCs could be used to develop, test, debug and port such codes. Using Intel Flash memory cards in a 80C186 based embedded system would address the issue of porting the code as well as overcoming the 1 Mbyte addressing constraint [2]. A simple implementation using Intel Flash memory cards in a 186 system is discussed here.

3. PCMCIA-186EA Interface:
The 80C186 family of microcontrollers are highly integrated 16-bit processors of choice for high performance embedded applicatons. 80C186EA is the second member of the 80C186 modular core family. It is 100% code compatible with standard 80C186 but includes two power management modes. Intel offers 80C186EA with an 8-bit data bus, the 80C188EA, as well as in 3V versions designated as the 80L186EA and 80L188EA. Upgrade's from the standard 80C186 applications to the 80C186EA microcontroller needs no software modifications and little or no hardware modifications in most cases and the details of upgrade are provided in AP-468 [3].
Intel's Series 2 Flash Memory Cards facilitate high-performance disk-emulation in mobile PCs and dedicated equipment [4]. Series 2 Flash Memory Cards conform to the Personal Computer Memory Card International Association (PCMCIA 2.0) / Japanese Electronics Industry Development Association (JEIDA 4.1) 68-pin standard, providing electrical and physical inter-compatibility. In addition, the Series 2 Flash Memory Card is compatible with Intel's Exchangeable Card Architecture (ExCA TM), an open hardware and software system implementation of PCMCIA Release 2.0 that allows inter-operatability from system-to-system independent of manufacturer.
The Flash Memory Card's low power consumption, transportability and compatibility make it an ideal choice for designers in the embedded market. Some embedded applications for which this product would be used is in the portable or handheld controllers, low power data acquisition and control systems (DAQM's), systems in harsh environments and systems that would benefit from solid state removable memory, to mention just a few. The targeted embedded markets, in general, are the one's where addressable memory has been a constraint or data is needed to be ported to other applications. The 80C186 family of microcontrollers is being used as the core processor in many embedded applications, however, the 80C186 can address a maximum space of 1 Mbyte directly thus limiting its usage in some applications. The addition of Flash memory cards would
further widen the application base of these controllers. Added with the power saving features of the 80C186EA, availability of the 3.3V powered 80L186EA and the power saving features of the Series 2 Flash Memory cards would definetly find wider application bases in embedded and industrial engineering.
In this example a simple paging scheme was used to increase the memory addressability of the 186 based platform. Page length was fixed to 64KBytes. The reasons for using the paging method are simplicity and ease. Also, 64KBytes is equal to the segmentation value in the 186 based systems as well as the page length of the Series 2 memory card. This makes it very attractive to have pages of 64KBytes each. The additional overhead added due to setting up of page is very small compared to the space which is made available for data storage or code execution and page set-up changes would be needed only while going to the next 64KByte boundary. For smoother execution of code, paging may not be the best solution, however, for the data storage, paging is one of the best solutions available.

4. Hardware :
The described add-in board increases the addressable memory space of both existing and future 80C186 platforms, with little modifications in some cases. Since the add-in would be based on Series 2 FLASH Memory Cards, the interface would meet the PCMCIA standard. Meeting the PCMCIA standard would increase the 80C186 memory space availability from 1 Meg to as high as 64 Meg . Other features include:

Figure 1. details the block diagram of the system. The map of memory and IO devices in this system is as shown in Figure 2. The system uses an 82510 as a serial controller to communicate to the outside world and 82C55, peripheral interface adapter, for memory paging. The system consists of :
4.1 Timing Analysis:
Series 2 Flash memory cards come in various read access times ranging from 150nS to 250nS. These times are referred only to the Read cycle and the Write cycle times are typically longer than the Read cycle times. 80C186EA cna be obtained in frequencies up to 20MHz which means
clock periods of 50nS (T=50nS).
Output enable(RD#) to data valid on the Series 2 cards is represented by t GLQV , which is a maximum of 100nS, and should be less than (2+n)T-TCLOV2-TCLIS of the 186EA, else would warrant wait ststes. Also, the address valid to data valid time for 186EA is (3+n)T-TCLOV2-TADLTCH-TCLIS which should be greater than the 250nS of the card's address access time, t AVQV. In the equation above n is the number of wait states to be inserted. With the insertion of each wait states the 186EA's timing would extend by a time equal to one T (50ns @ 20Mhz).
Hence a minimum of three Wait states would be necessary to gurantee reliable read operation for cards of speed up to 250nS using 186EA @ 20Mhz. Even with the card speeds of 150nS, would require one wait state for read operation while using the 186EA running at 20MHz. However, for write operation the same wait states would work fine as the write operation is done by polling the card to see whether the card is ready for next write.

4.2 PCIC Use:
Intel's PC Card Interface Controller (PCIC) - is the ExCA TM interface solution for the laptop PCs [5]. The 82365SL allows PC manufacturers to design their systems to provide the PC user with a wide range of connection or communication options (Modem, Twisted Pair Ethernet, etc.,) as well as eliminating rotating electromechanical media (via Intel Flash memory cards). In this design the 365SL was not used because of the following reasons:

4.3 PIA Use:
In this design, a cost effective and easy to implement solution is being suggested and implemented. This current design utilizes multiple ports to setup pages of 64K Bytes each. The primary page could be mapped to any available 64KBytes of the 186 memory space and then the consecutive pages can be set-up using the PIA. The parallel interface chosen for this application is Intel's 82C55, Programmable Peripheral Interface [6]. This CMOS device is very inexpensive and is easy to program making it a cost effective solution. However, using the 82C55 would definitely put some limitations on the proposed system. These limitations are:
5. Software:
Once the interface hardware was built, firmware was written to test and control the system functionality. This software allows the user to run various tests using a PC or a lap top. Software included initialization of the components of the system such as 82C55 and 82510
along with the 186. The flow chart of the system initialization and the interactive menu part of the software is as shown in Figure 3. Figure 4 shows the flow chart for the system initialization.
The serial controller 82510 is initialized for polled mode of operation as described in the application note AP-401 [7]. However, in order to address the 64MByte of the address space, the 186 system performs the following steps:
The above three step procedure has appropriate messages to indicate the actions taken . The messages are printed to the screen using the 82510 serial controller. However, the task of writing, reading or erasing the Flash memory card is accomplished by the special memory management software and the flow charts are as shown in Figures 5-8. Also, the system can detect the density and speed of the device for the Series 2 Flash memory cards.
One of the other advantages of adding these memory cards, as mentioned earlier, is the capability of developing and debugging x86 code remotely and then executing out of an existing platform or system. Also, as the card is memory mapped it is possible to simply add new features or change the existing software very easily either by using the card's memory or downloading to the system memory. Executing the code out of the PCMCIA card can be achieved in several ways such as FAR JUMPs, FAR CALLs or RETurn instruction execution [8].
a. FAR JUMP's can be used to achieve intra segment JUMP's in x86 code. This does not take up any stack space. Usage and syntax for such JUMP's are : JUMP FAR LABEL your_label. Where your_label is the user's chosen label. However, this does not allow a way to get back to the original location directly.
b. FAR CALL's are just like regular procedure calls but they allow intra-segment operability. However, the stack segment get's used and as usual 4Bytes are stored on the stack, which correspond to the present Code Segment (CS) and the Instruction Pointer (IP) value. Syntax for this instruction is: CALL PROC (FAR) or CALL DWORD PTR[reg16]. In this case a RET at the end will take you back to the previous code segment, if needed, as the information of the previous CS and IP are stored on the stack.
c. Using the RET instruction uses the stack temporarily, only to achieve the desired jump. The value desired of the CS and the IP are first stored on the Stack and then are restored to the present CS and IP with the Return instructiuon. Syntax is: RET.
The last method was used in this application and first the new IP and CS which correspond to the PCMCIA card page value (ie., CS=5000H and IP=0000H) were saved on the stack and a RET instruction was executed. This method, as mentioned before uses 4Bytes of space on the stack, temporarily. Now the code can be executed like any other segment with relocatable code being present on the memory card. Again the correct page has to be set-up before executing the RET instruction. At the end of the code segment again an another RET can be executed to get to the main program. The overhead of a few instructions compared to the 64KByte segment of code is very minimal and the performance degradation
is also negligible.

CONCLUSION:
This article details a 186-PCMCIA interface design and outlines the advantages in such a design.

References:
[1]. James D. Broesch, "Standard DOS tools to generate ROMable 80x86 code," EDN, Jan 7, 1993.
[2]. Embedded Microcontrollers and Processors, Vol II, Pg. 24-59 thru 24-173. Intel, 1993, Lit # 210830.
[3] Larry Bates, "Quick Upgrade from the 80C186 to the 80C186EA,", AP468, Intel, 1991, Lit#272157.
[4]. Memory Products, Series 2 Flash Memory cards, Intel, 1993 , Lit # 290434.
[5]. PC Card Interface Controller, Intel, 1993, Lit# 290423.
[6]. Peripherals Components, 3-124 thru 3-146, Intel, 1993, Lit # 231256.
[7]. Faisal Imdad-Haque, " Designing with the 82510 Asynchronous Serial Controller, " AP-401, Intel, 1993, Lit# 231928.
[8]. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Intel, 1986, Lit#210911.

Fig. 1. System Block Diagram.

(WELCOME TO PCMCIA-186 INTERFACE TO CHECK SYSTEM FUNCTIONALITY, ENTER ANY OF THE FOLLOWING CHOICES).

1. RAM TEST
2. READING FROM PCMCIA CARD
3. WRITING TO PCMCIA CARD
4. EXIT