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External Interrupt Controller Using Intel® 80310 I/O Processor Chipset
This document provides information to implement an external interrupt
controller when using the Intel® 80310 I/O processor chipset (80310),
which is composed of the Intel® 80200 processor based on Intel®
XScale™ Microarchitecture (ARM* architecture compliant) and the
Intel® 80312 I/O companion chip (80312). The 80312 does not provide
status and mask registers for the four external interrupt signals (XINT[3:0]#
and S_INT[D:A]#), therefore this document discusses some alternative
methods that need to be implemented in order to properly handle these interrupts.
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