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Low Pin Count Interface Specification
 
Overview

The Low Pin Count (LPC) Interface Specification for legacy I/O has facilitated the industry's transition toward ISA-less systems. The key enhancements to the 1.1 revision of the LPC Interface Specification is the inclusion of Firmware Memory cycles and addition of multibyte read capability.

The LPC Interface allows the legacy I/O motherboard components, typically integrated in a Super I/O chip, to migrate from the ISA/X-bus to the LPC Interface, while retaining full software compatibility. The LPC Specification offers several key advantages over ISA/X-bus, such as reduced pin count for easier, more cost-effective design. The LPC Interface Specification is software transparent for I/O functions and compatible with existing peripheral devices and applications.

The LPC Interface Specification describes memory, I/O and DMA transactions. Unlike ISA, which runs at 8MHz, it will use the PCI 33MHz clock and will be compatible with more advanced silicon processes. Mobile designers will also benefit from the reduced pin count because it uses less space and power and is more thermal efficient. The LPC Interface Specification Revision 1.1 and an associated reciprocal, royalty-free patent license agreement can be downloaded below.

download Download the Low Pin Count Interface Specification Agreement
lpc_lic.pdf
28 Kbytes

download Download the complete Low Pin Count Interface Specification
25128901.pdf
498 Kbytes

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