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- Overview
Intel® 5100 Memory Controller Hub Chipset for Embedded Computing Supporting Intel® Xeon® processor 5400/5300/5200/5100/3000 series
The power-optimized Intel® 5100 Memory Controller Hub (MCH) chipset supports development with high-performance, low-power Intel® multi-core processors, allowing bladed and dense bladed system designs to fit within a maximum 200-watt power envelope. Platform power savings is derived from lower thermal design power (TDP) in the MCH, a low-power Intel® I/O Controller Hub 9R (Intel® ICH9R), and standard native DDR2 memory technology. The Intel 5100 MCH chipset supports leading quad-core, dual-core, and single-core Intel® Xeon® processors in single- and dual-processor configurations, ranging from 1.6 GHz to 2.66 GHz core speed, with 30W to 65W TDPs.
This platform is ideal for a wide range of applications, such as storage area networks (SANs), network attached storage (NAS), routers, IP-PBX, converged/unified communications platforms, content firewalls, unified threat management (UTM) systems, medical imaging equipment, military signal and image processing, and telecommunications (wireless and wireline) servers - particularly in AdvancedTCA*.
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Product information
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Features and benefits
| Intel® Core™ Microarchitecture | Lower power quad-core, dual-core, and single-core Intel® Xeon® processors reduce cooling challenges and improve performance per watt for thermally constrained applications. |
|---|---|
| Native DDR2 registered DIMM technology |
Six slots supporting configurable low power DDR2 memory, with a maximum capacity of 48 GB. Fast speed memory operating at 533/667 MHz. Registered ECC DIMMs help protect data and improve reliability. |
| Intel® Virtualization Technology (Intel® VT)¹ | A processor hardware enhancement that assists virtualization software to deliver more efficient virtualization solutions and greater capabilities, including 64-bit guest OS support. |
| PCI Express* |
The Intel® 5100 MCH chipset supports six x4 PCIe* links. Each x4 link may be combined into three x8 links or one x16 link for configuration flexibility. The Intel® ICH9R supports six x1 lanes that can be combined into one x4 and two x1 links, or six x1 links. |
| Memory Reliability, Accessibility and Serviceability (RAS) features |
Front side bus address, data, and command parity increase system reliability and availability. Demand and patrol scrubbing proactively searches system memory, repairing correctable errors for enhanced system reliability. Optional memory sparing swaps "defective" DIMMs with installed but otherwise unused DIMMs for improved availability. x4 Single Device Data Correction (SDDC) can repair a failed x4 DRAM device on-the-fly, utilizing advanced ECC capabilities. Error correcting code corrects single-bit and detects double-bit errors. |
Packaging information
| Product | Package |
|---|---|
| Intel® 5100 Memory Controller Hub Chipset | 1432 Flip Chip-Ball Grid Array (FC-BGA) |
| Intel® 82801IR I/O Controller Hub 9R (ICH9R) | 676 Flip Chip-Ball Grid Array (FC-mBGA) |
¹ Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and applications enabled for virtualization technology. Functionality, performance or other virtualization technology benefits will vary depending on hardware and software configurations. Virtualization technology-enabled BIOS and VMM applications are currently in development.