|
|
|
 |
|
 |
|
 Intel has initiated a product discontinuance cycle for the Intel® 450NX PCIset.
The Intel® 450NX PCIset is a purpose-built chipset, architected for enterprise-class servers.
It provides an integrated Host-to-PCI bridge and memory controller optimized for 4-way multiprocessing standard high-volume (SHV) servers based on the Intel® Pentium® II Xeon® and the Intel® Pentium® III Xeon® processors. The 450NX PCIset contributes to a balanced platform by balancing the performance and the capabilities of the processor, I/O subsystems, L2 cache and main memory. A balanced server platform optimizes the benefits of each component to boost the overall system performance.
The 450NX PCIset enables the 4-way SHV server to reach new performance levels with the Pentium III Xeon processor. This performance SHV server takes advantage of the full capabilities of the 450NX PCIset featuring support up to 8 Gbytes of main memory and a flexible I/O subsystem, capable of either 4x32-bit, or 2x64-bit, 33MHz PCI buses, depending upon system manufacturer design implementation. The 450NX Basic configuration enables the 4-way SHV server to reach new lower-cost price points. This value SHV server uses a subset of the 450NX chipset to feature up to 4 Gbytes of main memory support and 2x32-bit, 33 MHz PCI buses. |
|
|
|
The 450NX PCIset consists of four components: 82451NX Memory and I/O Bridge Controller (MIOC), 82454NX PCI Expander Bridge (PXB), 82452NX RAS/CAS Generator (RCG), and 82453NX Data Path Multiplexor (MUX).
Memory and I/O Bridge Controller (MIOC)
The MIOC contributes to a balanced platform by directing traffic among the 100 MHz system bus, PCI buses and memory. It accepts access requests from the system bus and directs those accesses to memory or one of the PCI buses. The MIOC also accepts inbound requests from the PCI buses. The MIOC provides the data port and buffering for data transferred between the system bus, PXBs and memory. In addition the MIOC generates the appropriate controls to the RCG and MUX components to control data transfer to and from the memory.
PCI Expander Bridge (PXB)
The PXB takes information from the I/O subsection of the MIOC and distributes it to the PCI buses. Each PXB provides the interface to two independent 32-bit, 33 MHz Rev 2.1-compliant PCI buses, or a single 64-bit, 33 MHz Rev. 2.1-compliant PCI bus. The PXB is both a master and target on each PCI bus.
RAS/CAS Generator (RCG)
The RCG is responsible for accepting memory requests from the MIOC and converting these into the specific signals and timings required by the DRAM. Each RCG controls up to four banks of memory.
Data Path Multiplexor (MUX)
The MUX provides the multiplexing and staging required to support memory interleaving between the DRAMs and the MIOC. Each MUX provides the data path for one-half of a Quadword for each of four interleaves. |
|
|
|
|
 |
The system bus interface supports up to four Intel® Pentium® III Xeon® processors at a bus speed of 100 MHz. |
|
|
An additional bus mastering agent such as a cluster bridge can be supported at reduced frequencies to provide 8-way and beyond clustered servers for scalability with maximum headroom. |
|
|
The high-performance memory system, including card-to-card interleaving (C2C) and Address Bit Permuting (ABP), provides sufficient bandwidth to support four processors as well as high-bandwidth I/O traffic demanded by enterprise applications. |
|
|
|
|
|
|
The Intel 450NX PCIset supplements the reliability features of the Pentium III Xeon processor to support the platform reliability required by enterprise class and mission critical server applications. The Intel 450NX PCIset performs data checking at 3 main junctures of data transfer:
|
|
Between the MIOC and system bus via ECC coverage, and parity coverage of system bus controls |
|
|
Between the MIOC and Memory subsystem via ECC coverage of memory |
|
|
Between the MIOC and PCI Expander bridge via parity coverage of PCI bus and MIOC/PXB expander bus |
|
|
|
|
|
A complete 450NX PCIset with 2-RCGs, 4-MUXs, 2-PXBs and 1-MIOC dissipates a maximum of 47 watts at its 3.3V operating range.
|
|
MIOC - 540 lead PLGA. |
|
|
PXB - 540 lead PLGA. |
|
|
RCG - 324 lead PLGA. |
|
|
MUX - 324 lead PLGA. |
|
|
|
|
|
IEEE 1149.1 Standard Test Access Port and Boundary Scan mechanism enables testing of the Intel 450NX PCIset and system connections through a standard interface.
|
|
|
|
|
Chipset presents one electrical load to system bus. |
|
|
Supports the PIIX3 and PIIX4E south bridges which support: a PCI-to-ISA Bridge, support for USB, an enhanced DMA controller, system timer and IDE controller. |
|
|
|
|
|
|
|
|
Optimized for multiprocessor systems and standard high-volume (SHV) servers based on the Pentium III Xeon processor member of the P6 microarchitecture family. |
|
|
Available in 2 configurations: 450NX and 450NX Basic. |
|
|
Offers support for a third party controller such as a cluster controller for greater than 4-way processing. |
|
|
Supports system memory up to 8 Gbytes. |
|
|
Supports 16 Mbit and 64 Mbit, 60nsec and 50nsec, 3.3v EDO DRAM devices. |
|
|
Optimizes memory bandwidth via Address Bit Permuting (ABP), Card to Card (C2C) interleaving, and 4-way interleaved memory providing up to 1 Gbyte per second of memory bandwidth. |
|
|
I/O Expandable to support up to 4x32-bit PCI buses, 2x64-bit PCI buses, or 1x64-bit and 2x32-bit, Revision 2.1-compliant, PCI buses. |
|
|
Performance counters provide means of accumulating performance data for tuning of enterprise applications. |
|
|
Full Pentium III Xeon processor bus interface (36-bit address, 64-bit data) at 100 MHz. |
|
|
Separate reliability checking of data at all points of transfer: ECC coverage of processor data bus and memory, parity coverage of system bus controls, PCI bus and MIOC/PXB Expander Bus. |
|
|
|
|
|
|  | |
|
