Software and Hardware Considerations for FPU Exception Handlers for Intel Architecture Processors

The primary purpose of this application note is to provide information to help software engineers write the most robust Floating-Point Unit (FPU) exception handlers possible. This note also provides the basic hardware information needed to design the MS-DOS* compatible interface for the most recent generations of Intel Architecture processors, starting with the Intel486 processor. (Because of the small amount of new design activity, the hardware interfaces for the 8086 through the Intel386 processors are treated only briefly.) The third purpose is to provide a compendium of the history of the development and variations of the Intel Architecture Floating-Point Units (FPUs) as relevant to their exception handling.

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