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82091AA: Designing with the Shared IDE and Floppy Register

IDE hard disk drives and floppy disk controllers both decode the register 3F7h during reads. The floppy disk controller uses bit 7, the Disk Change bit, and tri-states the lower seven bits. The ATA IDE spec defines bits 6-0 as the Drive Address register and tri-states the seventh bit. BIOS vendors and application writers have been aware of the potential problems with this register, see the note about the IDE Drive Address Register at the bottom.

Floppy, Digital Input Register
3F7h, read only

DSKCNG - - - - - - -
7 6 5 4 3 2 1 0
DSKCNG

This bit reflects the opposite of the pin DSKCHG#

(-) means tri-state

IDE, Drive Address Register
3F7h, read only

7 6 5 4 3 2 1 0
- nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0
nWTG: write gate bit, set to 1 during write command
nHS[3:0]: one's complement of the binary-coded address of the currently selected head
nDS[1:0]: drive select bit for the master and slave drive
(-) means tri-state
Recommended Design

Since the 82091AA contains both a floppy disk controller and an ATA IDE interface, it decodes a chip select for both during a 3F7 read access. The data paths of these can be merged and then buffered to the system bus. The data enable pin (DEN#) on the 82091AA becomes active for all the enabled 82091AA modules. When a read of 3F7h occurs, the IDE drives the lower seven bits and the 82091AA drives the eighth bit (DB7). This byte is transferred through a buffer on to the ISA bus.

Figure 1. Merged Data Example
Commonly Asked Questions about the Merged Data Architecture

Figure 1.1 Merged Data Example without IDE Support1. What if I want to use the 82091AA without the IDE support?
Simply connect the 82091AA directly to the data bus. The 82091AA provides 24mA drive, so no external buffers are needed. The 82091AA will only drive data bit 7 on a read of the register 3F7h. All other bits will be tri-state. This is appropriate for local bus IDE applications, or applications where another IDE controller is preferred.

2. What if I want to add a SCSI drive to the system?
No problem, SCSI uses different addresses than IDE, no conflict should occur. Disable the IDE drive on the 82091AA via the configuration registers or via jumpers (hardware configuration modes).

3. What if the SCSI controller card has a floppy disk controller?
Simply disable the floppy and IDE on the 82091AA.

4. What if I want to add a local bus IDE drive?
Most all of the VL based local IDE controllers have an input pin for DSKCHG (disk change). This needs to be supplied from the floppy disk controller. To provide this, most VL based add-in cards come with a floppy disk controller. In this case disable the floppy disk controller and IDE on the 82091AA. If you are making an add-in card, the DSKCHG (Disk Change) bit is available from the floppy interface and connect the 82091AA's data bus directly onto the ISA bus.

5. What if I want to add another ISA based IDE controller?
Place it in the secondary address range (170-17Fh). There is no shared address in this configuration.

6. What if I want to add another ISA based IDE controller in the primary address space?
Most every ISA base IDE add-in card comes with a floppy disk controller. Disable the IDE controller and the floppy disk controller on the 82091AA and enable the floppy and IDE on the new controller.

Designs that must provide a replacement primary IDE controller without a new floppy disk controller can be designed as below (figure 2). This does not provide the 3F7h data from the IDE (see note about IDE Data Address Register, below), but does not contend with another primary IDE controller when disabled.

Figure 2
A Note About the IDE Drive Address Register

Significant testing on several platforms have show that these bits (from the IDE) are not used. Several IDE drive and BIOS vendors have been aware of this shared register and have avoided the issue by not writing code to utilize the IDE information in this register. The data provided by this register (head select and drive select) is available from other means in the status register and command status returned through the data register.

To be sure, review your BIOS code to see if this register is ever used. We have tested this on a wide variety of applications and have found no issues. Any application that is IBM PS/2 or Model 30 compatible must not use this register since it is not available in these modes.

The lower byte can be buffered independently. This is only necessary if: another IDE controller is required (without the floppy controller) and that controller can not be operated in the secondary address range and the BIOS (or applications) need the data bits from the IDE 3F7h register. This requires an extra buffer to divide the data bits.

Figure 3. Individually Buffered Data Bit 7
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