Systems that have the FIFO enabled or are using demand mode DMA transfers do not need to observe this timing specification. The falling edge of the DACK# removes the DRQ. However, the internal sampling circuitry of the 82077SL requires at least t23a time to ensure that a valid DACK# has been asserted. If the system is in violation of the t23a timing the 82077SL may raise an additional DRQ before the previous DACK# has been acknowledged and result in a mismanaged DMA transfer.
The worst case timing for t23a is at the 250 Kbps data rate. At this data rate, the minimum time required from the active edge of the DRQ to when the DACK# signal is inactive is 333 ns. Note that t23a includes DMA latency. Systems using 82077SL must allow at least 333 ns for t23a timing provided the system is running a single byte DMA write cycle with the FIFO disabled. If the system can not meet this timing, the problem can be solved by enabling the FIFO with a threshold of one. This allows the design to retain the current DMA scheme and meet the specification.
Figure 1. t23a in a DMA timing