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82077 SL Power-on Reset Problem

This white paper deals with a problem related to systems which have slower h/w resets. The slower reset causes a problem with the internal power-on and reset circuitry. This problem was discovered in the 82077SL (C-0) step recently. It is also possible to get into this condition on the prior steppings of the 82077SL and 82077AA. When the problem occurs the system will not be able to access the floppy disk sub-system. Intel's new 82077SL (C-1) stepping will alleviate this problem on systems.

Current operation

The DSR register contains two bits, PDOSC (bit 5) and PD (bit 6) which allow the user to turn off the internal oscillator and put the part in powerdown, respectively. The PDOSC bit turns off the internal oscillator and the PD bit turns off the schmitt trigger. Both the internal oscillator and the schmitt trigger generate signals to the internal clock generator. If these are turned off, the internal clock is not generated. The PDOSC bit is not present in the 82077AA . However, the PD bit is present in the current and previous steppings of both the 82077AA and 82077SL. The PDOSC bit was introduced in the 82077SL C-step to allow the user to turn off the internal oscillator if an external oscillator was being used and thus, increase power savings. The hardware pin reset signal is synchronized with the clock generator signal before being propagated to the rest of the chip. This synchronized hardware signal is also used to clear the registers such as DSR to their default state.

Problem description

The problem is related to the possibility that the two bits, PDOSC and PD in the DSR register become active during power-up and consequently disable the internal oscillator and clock generator. It should be clear from the above description of operation that this would in turn block the h/w reset from propagating. Since the hardware reset is required to clear these bits to an inactive state, there is an implicit race condition between the two bits becoming active during power-up and the h/w reset initializing them to an inactive state. If the bits become active before h/w reset clears them, the clock to the internal circuitry is blocked and no further commands to the 82077 will work. In order to exit from this state, it is necessary to disable the PDOSC and PD bits in the DSR register. Due the static nature of DSR, it can be accessed even during the problem condition and the bits can be disabled. This would allow the clock to be generated which will reactivate the internal circuitry. In addition to this a software reset can be executed (also via the DSR register) to clear some of the internal circuitry. However, there are several internal reinitializations done by the hardware reset that are not accomplished by the software resets. Since the power-on reset has already propagated in the system and is not regenerated, these modifications required at initialization will not be done. In particular, the 82077SL internally samples the IDENT and MFM pin level which is used to configure the operating mode (PC-AT, Model 30, PS/2) on the falling edge of h/w reset. However, since the h/w reset does not propagate, it could power-up in any state. This would cause problems if the user is using a particular mode. In addition, it could power up with the perpendicular mode or auto powerdown command enabled.


This problem is considered to be intermittent and random based on whether the h/w reset propagates or is blocked by the PDOSC and PD bits. Following are some of the different conditions depending on the particular implementation of the 82077 design:

a. The PDOSC bit has no effect if either an 82077AA is being used (the PDOSC bit is absent) or an external oscillator is being used with the 82077SL. Systems having either condition would have a lower chance of failure.

b. The probability of the problem decreases if the system has a fast h/w reset that ramps up along with VCC to the chip.

c. Laptops and portables that use zero-volt powerdown in which the VCC to the part is turned off are subject to higher number of failures. This can be eliminated by using the auto powerdown feature present in the part.

An effective workaround involves the following steps:

Disable the PDOSC and PD bits in the DSR by writing to this register.

Ensure that the clock is stable.

Issue a h/w reset.

It is recommended that the h/w reset to the 82077SL is kept active during the entire sequence. A secondary h/w reset can be generated from any extra port or register that is available on your particular system. This h/w reset is set and then disabled after it is ensured that the DSR register has been cleared and clock is stable. An external oscillator would give a fast stable clock. This sequence has to be carried out after any power-up or wakeup from a zero-volt powerdown.

82077SL C-1 stepping

The 82077SL (C-1) stepping has been modified to eliminate the problem. The h/w reset signal is not dependent on the clock in this design. This allows for h/w reset to propagate regardless of the state of the DSR bits. This would ensure that h/w reset disables PD and PDOSC. The h/w reset is synchronized on the falling edge, when the IDENT and MFM will be tested to enable the correct mode for the 82077SL.