This problem is considered to be intermittent and random based on whether the h/w reset propagates or is blocked by the PDOSC and PD bits. Following are some of the different conditions depending on the particular implementation of the 82077 design:
a. The PDOSC bit has no effect if either an 82077AA is being used (the PDOSC bit is absent) or an external oscillator is being used with the 82077SL. Systems having either condition would have a lower chance of failure.
b. The probability of the problem decreases if the system has a fast h/w reset that ramps up along with VCC to the chip.
c. Laptops and portables that use zero-volt powerdown in which the VCC to the part is turned off are subject to higher number of failures. This can be eliminated by using the auto powerdown feature present in the part.
An effective workaround involves the following steps:
Disable the PDOSC and PD bits in the DSR by writing to this register.
Ensure that the clock is stable.
Issue a h/w reset.
It is recommended that the h/w reset to the 82077SL is kept active during the entire sequence. A secondary h/w reset can be generated from any extra port or register that is available on your particular system. This h/w reset is set and then disabled after it is ensured that the DSR register has been cleared and clock is stable. An external oscillator would give a fast stable clock. This sequence has to be carried out after any power-up or wakeup from a zero-volt powerdown.