All of the 82355 EISA Interface signals with the exception of the data signals IDAT[31:0] and address signals IADS[31:10] are directly connected to the EISA bus. The 82355 uses seven TTL devices to interface to the EISA bus. The 82355 generates all the necessary control signals for these TTL devices.
The data lines IDAT[31:0] are connected to the EISA bus through four 74F245 data buffers (Figure 4). The 82355 generates control signals IDOE# and IDDIR for the 74F245 data buffers. The polarity of IDDIR signal forces the 74F245 A outputs (24ma) to be connected to the EISA bus, and the 74F245 B outputs (64ma) to be connected to the 82355. Although this configuration compiles with the EISA Bus Specifications for DATA current drive, it is recommended that the 74F245 B outputs (64ma) connected to the EISA bus. A 74F04 inverter in the IDDIR signal path allows for the 74F245 buffer output direction to be switch as recommenced (Figure 4).
Figure 4. EISA Interface Logic
Due to pin limitations on the package, the 82355 does not have dedicated output pins for EISA address lines IADS[31:0]. The 82355 uses IDATA[31:0] pins to multiplex the IADS[31:10] signals. Three 74F573 octal latches are required to latch addresses IADS[31:10] (Figure 4). The 82335 generates UALOE# signal as the latch input to the 74573s.
The 82355 takes advantage of the 1K page boundary defined in the EISA Bus Specifications to load the upper address IADS[31:10] in the 74F573 octal latches. Once the 82355 has been granted ownership of the EISA bus (MAK# asserted), the 82355 performs an upper address load cycle before starting data transfer (Burst or Non-Burst) on the EISA bus (Figure 5). Subsequently, during data transfer whenever a 1K page boundary is crossed, the 82355 will load the address of the new 1K page before proceeding with the data transfer.
Figure 5. EISA 1K Page Address Latch Cycle
The 82355 is a 32 bit Master device on the EISA bus and it can directly communicate with 32 bit EISA Slave devices. In the Burst mode, the 82355 can also directly communicate with 16 bit EISA Slave devices by downshifting into a 6 bit EISA Master. The 82355 communicates with 16 bit Non-Burst EISA Slaves and 8, or 16 bit ISA Slaves by allowing the EISA system board to copy the data and translate the control signals as necessary. The 82355 relinquishes the EISA bus to the EISA system board for data size translation as described in the following paragraph.
The 82355 initiates a data transfer cycle by asserting START# signal as always (Figure 6). The 82355 samples the EX32# signal and negates START# signal on the next rising edge of BCLK. A negated EX32# signal indicates to the 82355 to relinquish the control of the EISA bus to the EISA system board for data size translation. The 82355 starts to float START#, IBE#[3:0] and IDAT[31:0] (write) signals on the next following edge of BCLK. The EISA system board gains control of the EISA bus and performs the necessary data size translation cycles. The EISA system board relinquishes the EISA bus by asserting the EX32# signal. The 82355 samples the EX32# signal asserted on the rising edge of BCLK and regains control of the EISA bus on the next falling edge of BCLK.
Figure 6. Data Size Translation Cycle